View HMS91C71322_4213951.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

May. 2001
ver1.1
8-BIT SINGLE-CHIP MONITOR MICROCONTROLLERS
HMS9xC7132 HMS9xC7134
User's Manual
Version 1.1 Published by MCU Application Team bjinlim@hynix.com blackjoe@hynix.com
2001 HYNIX Semiconductor All right reserved.
Additional information of this manual may be served by HYNIX Semiconductor offices in Korea or Distributors and Representatives listed at address directory. HYNIX Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, HYNIX Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
HMS9xC7132 / HMS9xC7134
1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
13.2 Watchdog timer overflow . . . . . . . . . . . . . . . . . . . 37 13.3 Low VDD voltage reset . . . . . . . . . . . . . . . . . . . . 37
2. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . 2 3. PIN ASSIGNMENT . . . . . . . . . . . . . . . . . 3
3.1 40PDIP pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3.2 42SDIP pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
14. WATCHDOG TIMER . . . . . . . . . . . . . . 38 15. TIMER . . . . . . . . . . . . . . . . . . . . . . . . . 39
15.1 Timer0 and Timer1 . . . . . . . . . . . . . . . . . . . . . . . 39 15.2 TIMER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16. DDC INTERFACE . . . . . . . . . . . . . . . . 42
16.1 The SFRs for DDC Interface . . . . . . . . . . . . . . . . 43 16.2 DDC1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.3 DDC2B protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.4 DDC2AB/DDC2B+ protocol . . . . . . . . . . . . . . . . . 47 16.5 The RAM Buffer and DDC application . . . . . . . . . 48
4. PACKAGE DIMENSIONS . . . . . . . . . . . . 5
4.1 40 PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4.2 42 SDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
5. PIN FUNCTION . . . . . . . . . . . . . . . . . . . . 6
5.1 40DIP Pin Description . . . . . . . . . . . . . . . . . . . . . . .7 5.2 42SDIP Pin Description . . . . . . . . . . . . . . . . . . . . . .8
17. I2C INTERFACE . . . . . . . . . . . . . . . . . 51
17.1 The SFRs for I2C Interface . . . . . . . . . . . . . . . . . 52 17.2 Programmer's Guide for I2C and DDC2 . . . . . . . 54
6. PORT STRUCTURES . . . . . . . . . . . . . . . 9 7. ELECTRICAL CHARACTERISTICS . . . 11
7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .11 7.2 Recommended Operating Conditions . . . . . . . . . .11 7.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . .11 7.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .13
18. PULSE WIDTH MODULATION . . . . . . 57
18.1 Static PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 18.2 Dynamic PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
19. SYNC PROCESSOR . . . . . . . . . . . . . . 60
19.1 Sync input signals . . . . . . . . . . . . . . . . . . . . . . . . 60 19.2 Horizontal polarity correction . . . . . . . . . . . . . . . . 60 19.3 Vertical polarity correction . . . . . . . . . . . . . . . . . . 60 19.4 Vertical sync separation . . . . . . . . . . . . . . . . . . . . 60 19.5 Horizontal sync. detection . . . . . . . . . . . . . . . . . . 62 19.6 Vertical sync. detection . . . . . . . . . . . . . . . . . . . . 62 19.7 Horizontal sync. generator . . . . . . . . . . . . . . . . . . 65 19.8 Vertical sync. generator . . . . . . . . . . . . . . . . . . . . 66 19.9 HSYNC / VSYNC output driver . . . . . . . . . . . . . . 66 19.10 Clamp pulse generator . . . . . . . . . . . . . . . . . . . 67 19.11 Pattern generator . . . . . . . . . . . . . . . . . . . . . . . . 67 19.12 Suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8. MEMORY ORGANIZATION . . . . . . . . . 16
8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . .17 8.3 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8.4 List of SFRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.5 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . .22
9. INTERRUPTS . . . . . . . . . . . . . . . . . . . . 24
9.1 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . .24 9.2 Interrupt Enable structure . . . . . . . . . . . . . . . . . . .26 9.3 Interrupt Priority structure . . . . . . . . . . . . . . . . . . .27 9.4 How Interrupt are handled . . . . . . . . . . . . . . . . . . .29
10. POWER-SAVING MODE . . . . . . . . . . . 30
10.1 Power control register . . . . . . . . . . . . . . . . . . . . .30 10.2 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 10.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . .31
20. AD-CONVERTOR (ADC) . . . . . . . . . . . 71 21. OPERATION MODE . . . . . . . . . . . . . . 73
21.1 OTP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21.2 64MQFP pinning and Package Dimensions . . . . 78 21.3 64MQFP Pin Description . . . . . . . . . . . . . . . . . . . 79 21.4 Development Tools . . . . . . . . . . . . . . . . . . . . . . . 81
11. I/O PORTS . . . . . . . . . . . . . . . . . . . . . . 32
11.1 Pin function selection . . . . . . . . . . . . . . . . . . . . . .33
12. OSCIALLTOR . . . . . . . . . . . . . . . . . . . 36 13. RESET . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.1 External reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
22. INSTRUCTION SET . . . . . . . . . . . . . . . 82
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
HMS9xC7132 / HMS9xC7134
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR MONITOR
1. OVERVIEW
1.1 Description
The HMS9xC7132/4 is a single-chip microcontroller of the 80C51 family, which is dedicated for monitor application. It is particularly suitable for multi-sync computer monitor controller. This contains DDC interfaces to the PC host, sync-detector and sync-processor for auto-sync application, ADC, static PWM, dynamic PWM and I2C bus interface for control of the video and deflection functions of the monitor. Device name HMS91C7132/4 ROM Size 32K bytes Mask ROM RAM Size 512 bytes I/O 30(42DIP) 32(42SDIP) OTP HMS97C7132/4 Package 40DIP(HMS91C7132/4), 42SDIP(HMS91C7132/4K)
1.2 Features
* 80C51 core * 32K bytes of ROM for HMS91C7132/4 (32K bytes of OTP ROM for HMS97C7132/4) * 256 bytes of RAM and 256 bytes of XRAM for DDC operation * Uses an external crystal of 12 MHz * One DDC compliant interface : - Fully supports DDC1 with dedicated hardware - DDC2B, DDC2AB and DDC2B+ compliant dedicated hardware based on an I2C bus interface - RAM buffer with programmable size, 128 bytes or 256 bytes, which can be used for DDC operation or shared as system RAM * On-chip sync processor - HSYNC frequency with 12-bit resolution - VSYNC frequency with 12-bit resolution - HSYNC and VSYNC polarity - HSYNC and VSYNC presence detection - Composite sync separation - Free running sync. generation - Clamping pulse output - Pattern generation - Separate input for a SOG signal - Missing pulse insertion option - HSYNC/ VSYNC change interrupt * One multi-master/slave I2C interface (up to 400K bit/s) for control of other system IC's * Eight 8-bit Static PWM outputs for digital control applications * Two 8-bit Dynamic PWM outputs for various waveform generation * One 8-bit ADC with 4 input channels * LED driver port ; two port lines with 15 mA drive capability * One 8-bit port only for I/O function * 24 derivative I/O ports configurable for alternative functions * Watchdog timer (524ms max.) * On-chip low VDD voltage detect and reset (reset period: 524ms) * Operating temperature : 0 to 70 * Special idle and power-down modes with low power consumption * Single power supply : 4.5V to 5.5V
May.2001 ver1.1
1
2
IN T0 VDD1 VSS1 A CH[3:0] SDA2 SCL2 VDD2 V SS2 RE SET C PU Program M em ory (64K B ) D ata M em ory (64K B ) 8-B it ADC I2C -B us Serial I/O W atch D og T im er Sync. D etection & Sync. Process DDC Interface 8x8-B it Static PW M 2x8-B it D ynam ic PW M L ow V oltage R eset P3 SDA1 SCL1 PA TO U T CLA M P H SY N Cout V SY N Cout V SY N Cin H SY N Cin SO G in PW M 0 to PW M 7 DPW M0 to DPW M1
2. BLOCK DIAGRAM
80C 51 core
HMS9xC7132 / HMS9xC7134
X TA L1
X TA L2
T hree 16-B it T im ers ( T0, T1, T 2 )
Parallel I/O Ports & E xternal B us
P0
P1
P2
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
3. PIN ASSIGNMENT
3.1 40PDIP pinning
PWM0* /P2.2 DPWM0* /P2.1 DPWM0* /P2.0 RESET VDD1 VSS1 XTAL2 XTAL1 SDA2** /P1.7 SCL2** /P1.6 P0.7** P0.6** P0.5** P0.4** INT0/VPP P0.3** P0.2** P0.1** P0.0** ACH3 /P1.5
40DIP (Top View)
* : Open-drain option ** : Open-drain type pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vsync-IN Hsync-IN PWM1* /P2.3 PWM2* /P2.4 PWM3* /P2.5 PWM4* /P2.6 PWM5* /P2.7 Hsync-OUT /P3.2 Vsync-OUT /P3.3 PWM6* /INT1 /P3.4 CLAMP/PWM /P3.5 PADOUT /P3.6 SOG /P3.7 VDD2 VSS2 SCL1** /P1.0 SDA1** /P1.1 ACH0 /P1.2 ACH1 /P1.3 ACH2 /P1.4
HMS9xC7132
40DIP (Top View)
* : Open-drain option ** : Open-drain type pin
PWM0* /P2.2 DPWM0* /P2.1 DPWM0* /P2.0 RESET VDD1 VSS1 XTAL2 XTAL1 SDA2** /P1.7 SCL2** /P1.6 P0.7** P0.6** P0.5** P0.4** INT0/VPP P0.3** P0.2** P0.1** P0.0** ACH3 /P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vsync-IN Hsync-IN PWM1* /P2.3 PWM2* /P2.4 PWM3* /P2.5 PWM4* /P2.6 PWM5* /P2.7 Hsync-OUT /P3.2 Vsync-OUT /P3.3 PWM6* /INT1 /P3.4/CLAMP PWM /P3.5 PADOUT /P3.6 SOG /P3.7 P3.0 P3.1 SCL1** /P1.0 SDA1** /P1.1 ACH0 /P1.2 ACH1 /P1.3 ACH2 /P1.4
HMS9xC7134
May.2001 ver1.1
3
HMS9xC7132 / HMS9xC7134
3.2 42SDIP pinning
42SDIP (Top View)
* : Open-drain option ** : Open-drain type pin
PWM0* /P2.2 DPWM0* /P2.1 DPWM0* /P2.0 P3.1 P3.0 RESET VDD1 VSS1 XTAL2 XTAL1 SDA2** /P1.7 SCL2** /P1.6 P0.7** P0.6** P0.5** P0.4** INT0/VPP P0.3** P0.2** P0.1** P0.0**
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Vsync-IN Hsync-IN PWM1* /P2.3 PWM2* /P2.4 PWM3* /P2.5 PWM4* /P2.6 PWM5* /P2.7 Hsync-OUT /P3.2 Vsync-OUT /P3.3 PWM6* /INT1 /P3.4 CLAMP/PWM /P3.5 PADOUT /P3.6 SOG /P3.7 VDD2 VSS2 SCL1** /P1.0 SDA1** /P1.1 ACH0 /P1.2 ACH1 /P1.3 ACH2 /P1.4 ACH3 /P1.5
HMS9xC7132K
42SDIP (Top View)
* : Open-drain option ** : Open-drain type pin
NC PWM0* /P2.2 DPWM0* /P2.1 DPWM0* /P2.0 RESET VDD1 VSS1 XTAL2 XTAL1 SDA2** /P1.7 SCL2** /P1.6 P0.7** P0.6** P0.5** P0.4** INT0/VPP P0.3** P0.2** P0.1** P0.0** ACH3 /P1.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
NC Vsync-IN Hsync-IN PWM1* /P2.3 PWM2* /P2.4 PWM3* /P2.5 PWM4* /P2.6 PWM5* /P2.7 Hsync-OUT /P3.2 Vsync-OUT /P3.3 PWM6* /INT1 /P3.4/CLAMP PWM /P3.5 PADOUT /P3.6 SOG /P3.7 P3.0 P3.1 SCL1** /P1.0 SDA1** /P1.1 ACH0 /P1.2 ACH1 /P1.3 ACH2 /P1.4
HMS9xC7134K
4
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
4. PACKAGE DIMENSIONS
4.1 40 PDIP
0.550 0.530
2.075 2.045
MAX 0.200
NOTE 1. DIMENSIONS DO NOT INCLUDE MOLD FLASH AND DAMBAR PROTRUSION. ALLOWABLE MOLD FLASH IS 0.010 INCH. 2. CONTROLLING DIMENSION : INCH.
0.022 0.015 0.065 0.045
4.2 42 SDIP
0.550 0.530
1.470 1.450
NOTE 1. DIMENSIONS DO NOT INCLUDE MOLD FLASH AND DAMBAR PROTRUSION. ALLOWABLE MOLD FLASH IS 0.010 INCH. 2. CONTROLLING DIMENSION : INCH.
May.2001 ver1.1
5
HMS9xC7132 / HMS9xC7134
5. PIN FUNCTION
VDD1: Supply voltage (Digital). VSS1: Circuit ground (Digital). VDD2: Supply voltage (Analog). VSS2: Circuit ground (Analog). RESET: Reset the MCU. XTAL1: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XTAL2: Output from the inverting oscillator amplifier. HSYNCIN: Horizontal sync input VSYNCIN: Vertical sync input INT0/VPP: External Interrupt input. Programming supply voltage(during OTP programming) PORT: The HMS9xC7132 has four 8-bit ports (Port0, Port1, Port2, and Port3). Port0 - Port3 are the same as in the 80C51, with the exception of the additional functions of Port1, Port2 and Port3. Each has latch, SFR P0~P3' output driver and input buffer. P0.0~P0.7: P0 is an 8-bit CMOS bidirectional I/O port. P0 pins have not pull-up resister and open-drain port. It has the capability of drive LED. However, while the alternative function is performed, the port type will remain the same. In case of application to extention of external memory, P0 outputted Write/Read byte and lower byte of external memory address. Therefore when it is used as normal I/O port, P0 is open-drain driver and when it used as bus port, P0 is 3-state driver. Port pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Alternate function No (Only for I/O No (Only for I/O No (Only for I/O No (Only for I/O No (Only for I/O No (Only for I/O No (Only for I/O No (Only for I/O function) function) function) function) function) function) function) function) Port pin P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 DPWM0* DPWM1* PWM0* PWM1* PWM2* PWM3* PWM4* PWM5* Alternate function P1.0~P1.7: P1 is an 8-bit CMOS bidirectional I/O port. Because P1 pins have pull-up resister, it is called as Quasi-Bidirectional port. Port pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Alternate function SCL1 (DDC-SCL) SDA1 (DDC-SDA) ACH0 ACH1 ACH2 ACH3 SCL2 (I2C-SCL) SDA2 (I2C-SDA)
P2.0~P2.7: P2 is an 8-bit CMOS bidirectional I/O port. Because P2 pins have pull-up resister, it is called as Quasi-Bidirectional port. .
P3.0~P3.7: P3 is an 8-bit CMOS bidirectional I/O port. Because P3 pins have pull-up resister, it is called as Quasi-Bidirectional port. Port pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate function Reserved Reserved HSYNCOUT VSYNCOUT PWM6* CLAMP/PWM7 PATOUT SOG
6
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
5.1 40DIP Pin Description
PIN NAME (Alternate) PWM0 /P2.2 DPWM0 /P2.1 DPWM0 /P2.0 RESET VDD1 VSS1 XTAL2 XTAL1 SDA2 /P1.7 SCL2 /P1.6 P0.7 P0.6 P0.5 P0.4 INT0 /VPP P0.3 P0.2 P0.1 P0.0 ACH3 /P1.5 ACH2 /P1.4 ACH0 /P1.3 ACH0 /P1.2 SDA1 /P1.1 SCL1 /P1.0 VSS2 VDD2 SOGin /P3.7 PATOUT /P3.7 CLAMP /PWM7 / P3.5 /PROG PWM6 /P3.4 / INT1 VSYNCout /P3.3 HSYNCout /P3.2 PWM5 /P2.7 PWM4 /P2.6 PWM3 /P2.5 PWM2 /P2.4 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 In/Out (Alternate) I/O I/O I/O I O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Basic General I/O port P2.2 General I/O port P2.1 General I/O port P2.0 Reset input Power supply1(+5V) Ground1 Oscillator output pin for system clock Oscillator input pin for system clock General I/O port P1.7 General I/O port P1.6 I2C serial data I/O port I2C serial clock I/O port Alternate 8-bit Pulse Width Modulation output0 8-bit Dynamic Pulse Width Modulation output0 8-bit Dynamic Pulse Width Modulation output1
General I/O port P0.7; adapted for LED driver General I/O port P1.6; adapted for LED driver General I/O port P0.5 General I/O port P0.4 External interrupt input0; Programming supply voltage (during OTP programming) General I/O port P0.3 General I/O port P0.2 General I/O port P0.1 General I/O port P0.0 General I/O port P1.5 General I/O port P1.4 General I/O port P1.3 General I/O port P1.2 General I/O port P1.1 General I/O port P1.0 Ground2 Power supply2(+5V) General I/O port P3.7 General I/O port P3.6 General output only port P3.5 Program pulse input(during OTP programming) General I/O port P3.4 General I/O port P3.3 General I/O port P3.2 General I/O port P2.7 General I/O port P2.6 General I/O port P2.5 General I/O port P2.4 Sync on Green input Pattern out Clamp out ; 8-bit Pulse Width Modulation output7 8-bit Pulse Width Modulation output6; External interrupt input1 Vertical sync output Horizontal sync output 8-bit Pulse Width Modulation output5 8-bit Pulse Width Modulation output4 8-bit Pulse Width Modulation output3 8-bit Pulse Width Modulation output2 ADC channel3 input ADC channel2 input ADC channel1 input ADC channel0 input I2C serial data I/O port for DDC interface I2C serial clock I/O port for DDC interface
31 32 33 34 35 36 37
I/O I/O I/O I/O I/O I/O I/O
Table 5-1 Port Function Description(40DIP)
May.2001 ver1.1
7
HMS9xC7132 / HMS9xC7134
PIN NAME (Alternate) PWM1 /P2.3 HSYNCin VSYNCin
Pin No. 38 39 40
In/Out (Alternate) I/O I I
Function Basic General I/O port P2.3 Horizontal sync input Vertical sync input Table 5-1 Port Function Description(40DIP) Alternate 8-bit Pulse Width Modulation output1
5.2 42SDIP Pin Description
The 42SDIP type pin description is the same as The 40DIP type pin description except for adding two pins(P3.1, P3.0) to it between pin no.4 and 5.
8
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
6. PORT STRUCTURES
P0.0 - P0.5 P0.6 - P0.7
data
data
5mA
10mA
CMOS
CMOS
P1.0, P1.1, P1.6, P1.7, P2.0~7, P3.0, P3.1, P3.4, P3.6
P1.2 - P1.5
oen
oen
data
data
adc_in
CMOS
CMOS
adc_enb
P3.2, P3.3, P3.5
P3.7
internal reset
oen
data
data
TTL
TTL
May.2001 ver1.1
9
HMS9xC7132 / HMS9xC7134
HSYNCIN, VSYNCIN
INT0/VPP
TTL
TTL H
VPP detector VPP
RESET
XTAL1, XTAL2
CMOS
pdb
10
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage......................................................-0.5 to +6.5 V Storage Temperature .......................................... -65 to +150 C Voltage on any pin with respect to Ground (VSS) ..........................................................................-0.5 to VDD +0.5
mum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: Stresses above those listed under "Absolute Maxi-
7.2 Recommended Operating Conditions
Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition fXIN=12MHz VDD=4.5~5.5V Specifications Min. 4.5 10 0 Max. 5.5 16 70 Unit V MHz C
7.3 DC Electrical Characteristics
(TA= 0~70C, VDD=4.5~5.5V, VSS=0V ), Symbol SUPPLY VDD IDD VLVR OTP SUPPLY VDD VPP IDDP IPP RESET IRST IIH VIL1 VIH1 XTAL VOP IFR VIL1 VIH1 IIL IIH VIL open bias voltage feedback resistor current LOW-level input voltage HIGH-level input voltage input leakage current input leakage current LOW-level input voltage VIN - 5V VIN - VSS VIN - VDD VSS-0.5 0.7VDD -1 VSS-0.5 2.5 10 0 0 0.3VDD VDD+0.5 1 0.3VDD V A V V A A V RESET input pull-up resistance VIN - 0V input leakage current LOW-level input voltage HIGH-level input voltage VIN - VDD -
Parameter
Condition
Specifications Min. 4.5
-
Typ. 5.0 TBD 3.7 5.0 12.75 TBD TBD 33 0 -
Max. 5.5
-
Unit
power supply voltage power supply current low voltage reset power supply voltage programming voltage power supply current programming current
Fosc - 12MHz Fosc - 4MHz Fosc - 4MHz
V mA V V V mA mA A A V V
3.3 4.5 -
4.1 5.5 -
1 0.3VDD VDD+0.5
VSS-0.5 0.7VDD
INT0, HSYNCIN, VSYNCIN
May.2001 ver1.1
11
HMS9xC7132 / HMS9xC7134
Symbol VIH SOG/P3.7 IIL1 ITL IIH VIL VIH VOL VOH P0.0 to P0.5 IIL IIH VIL1 VIH1 VOL P0.6 to P0.7 IIL IIH VIL1 VIH1 VOL1 IIL1 ITL1 IIH VIL1 VIH1 VOL VOH IIL1 ITL1 IIH VIL1 VIH1 VOL VOH IIL2 ITL2 IIH VIL VIH
Parameter HIGH-level input voltage input leakage current input transition current input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level input voltage input leakage current input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage input leakage current input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage input leakage current input transition current input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level input voltage input leakage current input transition current input leakage current LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level input voltage input leakage current input transition current input leakage current LOW-level input voltage HIGH-level input voltage -
Condition
Specifications Min. 2.0 -55 -650 VSS-0.5 2.0 0 3.5 -1 VSS-0.5 0.7VDD 0 -1 VSS-0.5 0.7VDD 0 -55 -650 VSS-0.5 0.7VDD 0 3.5 -55 -650 VSS-0.5 0.7VDD 0 3.5 -960 -1240 0 VSS-0.5 2.0 Typ. 0 0 0 0 0 0 0 Max. VDD+0.5 -10 -65 1 0.8 VDD+0.5 0.4 VDD 1 0.3VDD VDD+0.5 0.4 1 0.3VDD VDD+0.5 0.4 -10 -65 1 0.3VDD VDD+0.5 0.4 VDD -10 -65 1 0.3VDD VDD+0.5 0.4 VDD -320 -350 1 0.8 VDD+0.5
Unit V A A A V V V V A A V V V A A V V V A A A V V V V A A A V V V V A A A V V
VIN - 0.45V VIN - 2.0V VIN - VDD IOL - 5mA IOH - 5mA VIN - VSS VIN - VDD IOL - 5mA VIN - VSS VIN - VDD IOL - 10mA VIN - 0.45V VIN - 3.5V VIN - VDD IOL - 5mA IOH - 5mA VIN - 0.45V VIN - 3.5V VIN - VDD IOL - 5mA IOH - 5mA VIN - 0.45V VIN - 2.0V VIN - VDD -
P2.0 to P2.7(BP2.0 to BP2.7)
P1.0 to P1.7,P3.0,P3.1,P3.4,P3.6,P3.7
P3.2 to P3.3,P3.5
12
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Symbol VOL VOH
Parameter LOW-level output voltage HIGH-level input voltage IOL - 5mA IOH - 5mA
Condition
Specifications Min. 0 3.5 Typ. Max. 0.4 VDD
Unit V V
7.4 AC Characteristics
(TA=-0~70C, VDD=5.0V, VSS=0V) Symbol XTAL fosc C1 C2 A/D Converter VAIN nAOFF nFS nACC tCONV DDC1 Mode tH(VCLK) tL(VCLK) tDOV tSU(DDC1) tNC(IN) DDC2 Mode fSCL tHD(SDA) tSU(STO) tHD(DAT) tSU(STA) tH(SCL) tL(SCL) HSYNCin f(HSYNC) tW(HSYNC) d(HSYNC) VSYNCin f(VSYNC) tW(VSYNC) d(VSYNC) SOGin VSYNC input frequency VSYNC input pulse width VSYNC duty cycle 32 1 200 24 25 Hz tP(H) % HSYNC input frequency HSYNC input pulse width HSYNC duty cycle 12 0.25 120 8 25 kHz s % SCL clock frequency Start condition hold time Stop condition setup time Data hold time Rstart(1) condition setup time SCL high period SCL low period 0 4.0 4.0 300 4.7 4.0 4.7 100 kHz s s s s s s VCLK high time VCLK low time VCLK to output valid DDC1 mode setup time cancelled noise input fosc - 12MHz fosc - 12MHz 20 20 TBD 680 300 sV s s s s analog input voltage zero offset error full scale error overall accuracy conversion time fosc - 12MHz VSS 20 13 VDD TBD TBD TBD V LSB LSB LSB s oscillator frequency xtal1 external Cap. xtal2 external Cap. VDD - 5V 10 12 20 20 16 MHz pF pF Parameter Condition Specifications Min. Typ. Max. Unit
May.2001 ver1.1
13
HMS9xC7132 / HMS9xC7134
Symbol tP(EQ) tW(EQ) n(EQ) tD(HSYNC) tD,MAX(HSYNC) tD(HSYNC) tD,MAX(VSYNC) tD(CLAMP)
Parameter equalizing pulse period equalizing pulse width equalizing pulse interval HSYNC input to output HSYNC input to output after missing HSYNCin VSYNC input to output VSYNC input to output after missing VSYNCin HSYNCin to CLAMP -
Condition
Specifications Min. Typ. 0.5 0.5 Max. 30 100 250 180 1 100
Unit tP(H) tW(H) tP(H) ns ns ns tP(H) ns
HSYNCout, VSYNCout
14
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
SDA
SCL
tHD(SDA)
tHD(DAT)
tSU(DAT)
tSU(STA) tSU(STO)
Figure 7-1 timing on the I2C-bus
HSYNCin
tW(HSYNC)
HSYNCout
tD(HSYNC)
CLAMP (front porch)
tD,MAX(HSYNC)
CLAMP (back porch)
tD(CLAMP)
tD(CLAMP)
VSYNCin
tW(VSYNC)
VSYNCout
tD(VSYNC) Figure 7-2 SYNC timing
tD,MAX(VSYNC)
May.2001 ver1.1
15
HMS9xC7132 / HMS9xC7134
8. MEMORY ORGANIZATION
The HMS91C7132 has separate address spaces for Program memory, Data Memory. Program memory can only be read, not written to. It can be up to 32K bytes of Program memory.(OPT type: HMS97C7132 32K bytes) Data memory can be read and written to up to 256 bytes including the stack area.(Internal RAM) and 256bytes (External RAM: 256bytes of XRAM0).
RAM 255 Indirect only ("mov @ri") 32K ROM 127 Direct("mov") or Indirect ("mov @ri") 0 program memory
SFR Direct ("mov") or Indirect ("mov @ri" )
XRAM
Indirect ("movx @ri" or movx @dptr) (XRAMS = 0)
data memory
Figure 8-1 Memory map and address spaces
8.1 Registers
This device has several registers that are the Program Counter (PC), Accumulator (A), B register(B), the Stack Pointer (SP), the P rog ram St a tus W or d(P SW ), G ene ral pu rpo se reg ister(R0~R7)and DPTR(Data pointer register). and conditional judgement, etc. The Accumulator can be used as a 16-bit register with B Register as shown below.
B
A B SP PCH PCL PSW R0~R7 DPTR(DPH) DPTR(DPL) ACCUMULATOR B REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD GENERAL PURPOSE REGISTER (BANK0~3) DATA POINTER REGISTER
B
A
A
Two 8-bit Registers can be used as a "BA" 16-bit Register
Figure 8-3 Configuration of BA 16-bit Registers B Register: The B Register is the 8-bit purpose register, used for an arithmatic operation such as multiply, division with Accumulator Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be access (save or restore).The stack can be located at any position within 0000H to 007FH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with
Figure 8-2 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving,
16
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
which the use of the stack starts) by using the initialization routine. Normally, the initial value of "07H" is used and the stack area is 00H to 7FH .
Stack Area (30H ~ 7FH) Bit 15 87 00H SP Hardware fixed SP (Stack Pointer) could be in 00H~7FH.
This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Auxiliary carry flag AC] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. [Register bank select flags RS0, RS1] This flags select one of four bank(00~07H:bank0, 08~0fH:bank1, 10~17H:bank2, 17~1FH:bank3)in Internal RAM. [Overflow flag OV] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Parity flag P] This flag reflect on number of Accumulator's 1. If number of Acuumulator's 1 is odd, P=0. otherwise P=1. Sum of adding Acuumulator's 1 to P is always even. R0~R7: General purpose register. Data Pointer Register:Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This register is used as a data pointer for the data transmission with external data memory.
Bit 0 00H~7FH
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU and select Internal RAM(00H~1FH:Bank0~Bank3). The PSW is described in Figure 8-4. It contains the Carry flag, the Auxiliary carry flag, the Half Carry (for BCD operation), the General purpose flag, the Register bank select flags, the Overflow flag, the undefined flag and Parity flag. [Carry flag CY]
MSB PSW CARRY FLAG AUXILIARY CARRY FLAG GENERAL PURPOSE FLAG REGISTER BANK SELECT FLAG (to select Bank0~3 with RS0) CY AC F0 RS1 RS0 0V
LSB P RESET VALUE: 00H PARITY FLAG NOT ASSIGNED BIT OVERFLOW FLAG REGISTER BANK SELECT FLAG (to select Bank0~3 with RS1)
Figure 8-4 PSW(Program Status Word)Register
8.2 Program Memory
The program memory consists of ROM : 32K bytes (HMS91C7132) and 32K bytes (HMS97C7132)
8.3 Data memory
The internal data memory is divided into four physically separated part : 256 bytes of RAM, 256 bytes of XRAM0, and 128 bytes of Special Function Registers (SFRs) areas. RAM Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47,
May.2001 ver1.1
17
HMS9xC7132 / HMS9xC7134
contain 128 directly addressable bit locations.The stack depth is only limited by the available internal RAM space of 256 bytes. XRAM0 The 256 bytes of XRAM0 used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. The address pointer(DDCADR) is equipped with the postincrement capability to facilitate the transfer of data in bulk (for details refer to DDC Interface part). However, it is also possible to address the DRAM through MOVX command as usually used in the internal
RAM extension of 80C51 derivatives. XRAM0 0 to 255 is directly addressable as external data memory locations 0 to 255 via MOVX-DPTR instruction or via MOVX-Ri instruction when the EXCON's LSB is zero. Since external access function is not available, any access to XRAM0 0 to 255 will not affect the ports. 7 6 5 4 3 2 1 0
XRAMS
Table 8-1 Extended control Register(EXCON)
BYTE AD DR ESS (H E X ) FF H
B IT ADD R ESS (H E X )
BYTE ADDRESS (D E C IM A L) 2 55
(M S B )
(LS B )
~ ~
2F H 2E H 2D H 2C H 2B H 2A H 29 H 28 H 27 H 26 H 25 H 24 H 23 H 22 H 21 H 20 H 1F H 18 H 17 H 10 H 0F H 08 H 07 H 00 H 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
~ ~
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23 16 15 8 7 0
BANK3 BANK2 BANK1 BANK0
Figure 8-5 RAM ADDRESS
18
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
SFR The SFRs can only be addressed directly in the address range from 128 to 255. Table 8.2 gives an overview of the Special Function Registers space. Sixteen address in the SFRs space are bothbyte and bit-addressable. The bit-addressable SFRs are those whose address ends in 0H and 8H. The bit addresses in this area are 80H to FFH.
F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80
*B *EXCON *ACC *S1CON *PSW *T2CON *IP *P3 *IE *P2 *P1 *TCON *P0
HVGEN MDCON S1STA DPWMCON PWMCON P1SFS TMOD SP
CPGEN MDST S1DAT RC2L
VFH VPH
VFL HPH -
HFH VHPL S2STA DDCDAT -
HFL S2DAT DDCADR S2ADR DDCCON
FF F7 EF E7 DF D7 CF C7 BF
S1ADR0 S1SDR1 RC2H
S2CON RAMBUF -
DPWM0 PWM4 PWM0 P2SFS TL0 DPL
DPWM1 PWM5 PWM1 P3SFS TL1 DPH TH0 PWM6 PWM2
PWM7 PWM3
IPA WDTKEY WDTRST ADAT
IEA ACON PCON
B7 AF A7 9F 97 8F 87
TH1
Table 8-2 SFR Memory Map Note: * The register that can be bit-addressing.
May.2001 ver1.1
19
HMS9xC7132 / HMS9xC7134
8.4 List of SFRS
Register P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 P1SFS P2SFS P3SFS ADAT ACON P2 PWMCON PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 WDTKEY WDTRST IEA IE P3 DPWMCON DPWM0 DPWM1 IPA IP T2CON RC2L RC2H PSW RAMBUF Port0 Register Stack Point register Data Pointer(Low byte) Register Data Pointer(High byte) Register Power Control Register Timer/Counter Control Register Timer/Counter Mode Control Register Timer/Counter0 Low byte Register Timer/Counter1 Low byte Register Timer/Counter0 High byte Register Timer/Counter1 High byte Register Port1 Register Port1 Special Function Selection Register Port2 Special Function Selection Register Port3 Special Function Selection Register ADC Data Register ADC Control Register Port2 Register PWM Control Register PWM0 Output Register PWM1 Output Register PWM2 Output Register PWM3 Output Register PWM4 Output Register PWM5 Output Register PWM6 Output Register PWM7 Output Register Watchdog Key Register Watchdog Timer Reset Register Interrupt Enable Register Interrupt Enable Register Port3 Register Dynamic PWM Control Register Dynamic PWM0 Output Register Dynamic PWM1 Output Register Interrupt Priority Register Interrupt Priority Register Timer2 Control Register Reload Low Register Reload High Register Program Status Word Register RAM Buffer I/O Interface Register Description Address 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 91H 92H 93H 96H 97H 0A0H 0A1H 0A2H 0A3H 0A4H 0A5H 0AAH 0ABH 0ACH 0ADH 0AEH 0A6H 0A7H 0A8H 0B0H 0B1H 0B2H 0B3H 0B6H 0B8H 0C8H 0CAH 0CBH 0D0H 0D4H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value
76543210
11111111 00000111 00000000 00000000 xx000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 00000000 00000000 00000000 00000000 xx0x0001 11111111 00000000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 00000000 00000000 0xxxxx00 00000000 11111111 0xxxxx00 11111111 11111111 0xxxxx00 x0000000 0xxxx0xx 00000000 00000000 00000000 xxxxxxxx
20
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Register DDCDAT DDCADR DDCCON S1CON S1STA S1DAT S1ADR0 S1ADR1 S2CON S2STA S2ADR S2DAT ACC EXCON B MDCON MDST VPH HPH VHPL HVGEN CPGEN VFH VFL HFH HFL
Description Data Shift Register for DDC1 DDC Address Pointer Register DDC Mode Status and DDC1 Control Register Serial Control Register for DDC2 Serial Status Register for DDC2 Data Shift Register for DDC2 Serial Address0 Register for DDC2 Serial Address1 Register for DDC2 Serial Control Register Serial Status Register Serial Address Register for I2C Data Shift Register for I2C Accumulator Extended Control Register B Register Mode Indication Register Mode Status Register Vertical scan period High byte Register Horizontal scan period High byte Register V/H scan period High byte Register H/V pulse Control Register Clamping pulse and Pattern Control register Vertical free-running output pulse period High byte register Vertical free-running output pulse period Low byte register Horizontal free-running output pulse period High byte register Horizontal free-running output pulse period Low byte register
Address 0D5H 0D6H 0D7H 0D8H 0D9H 0DAH 0DBH 0D3H 0DCH 0DDH 0DFH 0DEH 0E0H 0E8H 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH
R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value
76543210
00000000 00000000 x00x0000 00000000 0x00xxxx 00000000 0000000x 0000000x 00000000 0x00xxxx 0000000x 00000000 00000000 xxxxxxx0 00000000 000xx000 x0000000 00000000 00000000 00000000 x000x000 00000x00 00100000 00001010 01100000 00x11111
May.2001 ver1.1
21
HMS9xC7132 / HMS9xC7134
8.5 Addressing Mode
The addressing modes in HMS9xC7132 instruction set are as follows
* Direct addressing * Indirect addressing * Register addressing
* Register-specific addressing * Immediate constants addressing * Indexed addressing
Note that refer to "Chapter 22. Instruction Set" those addressing modes and related instructions.
(1) Direct addressing
In a direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal D ata RAM and SFRs(80~FFH RAM) can be directly addressed. Example: mov A, 3EH ;A
PROG. MEMORY
RAM[3E]
3EH
04
A
(2) Indirect addressing
In indirect addressing the instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit "data pointer" register, DPTR. Example: mov @R1, 40H ;[R1]
PROG. MEMORY
40H
55
H]
~ ~
R1 55
~ ~
(3) Register addressing
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of four banks is selected at execution time by the two bank select bits in the PSW. Example; mov PSW, #0001000B ; select Bank0 mov A, #30H mov R1, A
(4) Register-specific addressing
Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is needed to point it. The opcode itself does that.
22
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
(5) Immediate constants addressing
The value of a constant can follow the opcode in Program memory. Example; mov A, #100H.
(6)Indexed addressing
Only Program memory can be accessed with indexed addressing, and it can only be read. This addressing mode is intended for reading look-up tables in Program memory. A 16-bit base register (either DPTR or PC) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program memory is formed by adding the Accumulator data to the base pointer. Example; movc A, @A+DPTR
ACC 3A
DPTR 1E73
PROG. MEMORY
~ ~
~ ~
1EADH
May.2001 ver1.1
23
HMS9xC7132 / HMS9xC7134
9. INTERRUPTS
There are interrupt requests from 9 sources as follows.
* INT0 external interrupt * INT1 external interrupt *Timer0 interrupt * Timer1 interrupt * Timer2 interrupt
* DDC interrupt * MD interrupt * VSYNC interrupt * I2C interrupt
9.1 Interrupt sources
INT0 external interrupt: *The INT0 can be either level-active or transition-active depending on bit IT0 in register TCON. The flag that actually generates this interrupt is bit IE0 in TCON. * When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. * If the interrupt was level-activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
INT1 external interrupt: *The INT1 can be either level-active or transition-active depending on bit IT1 in register TCON. The flag that actually generates this interrupt is bit IE1 in TCON. * When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. * If the interrupt was level-activated then the interrupt request flag remains set until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
MD interrupt: *A MD interrupt is generated by the hardware mode detector in case of mode change, horizontal or vertical. * This flag has to be cleared by the software.
VSYNC interrupt: *The changing of the VSYNC level can generate an interrupt. This depends on the setting that is programmed in the MDCONSFR. Via this register it is possible to enable the edge of the VSYNC-signal that should generate the interrupt. Both edges can be controlled separately. * The interrupt flag has to be cleared by the software.
DDC interrupt: *The DDC interrupt is generated either by bit INTR in the S1STA register for DDC2B/DDC2AB/DDC2B+ protocol or by bit DDC_int in the DDCCON register for DDC1 protocol or by bit SWHINT bit in the DDCCON register when DDC protocol is changed from DDC1 to DDC2. * Flags except the INTR have to be cleared by the software. INTR flag is cleared by hardware.
I2C interrupt: *The interrupt of the second I2C is generated by bit INTR in the register S2STA. * This flag is cleared by hardware.
24
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Timer0 and Timer1 interrupt: *Timer0 and Timer1 interrupts are generated by TF0 and TF1 which are set by an overflow of their respective Timer/Counter registers(except for Timer0 in mode3). *These flags are cleared by the internal hardware.
Timer2 interrupt: *Timer2 interrupt is generated by TF2 which is set by an overflow of Timer2. * This flag has to be cleared by the software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software.
Interrupt Sources INT0
IE / IEA
IP / IPA
Priority
High Low
MD
Timer0
I2C Interrupt Polling Sequence Global Enable
INT1
DDC
Timer1
VSYNC Not used Timer2
Figure 9-1 Interrupt system
May.2001 ver1.1
25
HMS9xC7132 / HMS9xC7134
9.2 Interrupt Enable structure
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable special function register IE and IEA. All interrupt source can also be globally disabled by clearing bit EA in IE.
7 EA
6 EVSYNC
5 ET2
4 ES
3 ET1
2 EX1
2 ET0
0 EX0
Table 9-1 Interrupt Enable Register(IE: 0A8H) BIT SYMBOL
RESET VALUE:00000000B FUNCTION
Disable all interrupts.
7 EA
0 : no interrupt will be acknowledged 1 : each interrupt source is individually enabled or disabled by setting or clear ing its enable bit Enable Vsync interrupt Enable timer2 interrupt Not used Enable timer1 interrupt Enable external interrupt (INT1) Enable timer0 interrupt Enable external interrupt (INT0)
Table 9-2 Description of the IE bits
6 5 4 3 2 1 0
EVSYNC ET2 ES ET1 EX1 ET0 EX0
7 EDDC
6 -
5 -
4 -
3 -
2 -
2 EI2C
0 EMD
Table 9-3 Interrupt Enable Register(IEA: 0A7H)
RESET VALUE:0xxxxx00B
BIT 7 6 5 4 3 2 1 0
SYMBOL EDDC EX6 EX5 EX4 EX3 EX2 EI2C EMD
FUNCTION
Enable DDC interrupt Not used Not used Not used Not used Not used Enable I2C interrupt Enable MD interrupt
Table 9-4 Description of Enable Register(IEA: 0A7H)
26
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
9.3 Interrupt Priority structure
Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function register IP and IPA. "0" - low priority "1" - high priority A low priority interrupt may be interrupted by a high priority interrupt level interrupt. A high priority interrupt routine cannot be interrupted by any other interrupt source. If two interrupts of different priority occur simultaneously, the high priority level request is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence. This second priority structure is shown in Table 9.5.
SOURCE INT0 MD Timer0 I2C INT1 DDC Timer1 VSYNC Timer2
PRIORITY WITHIN LEVEL
1(highest)
9(lowest) Table 9-5 Priority levels
Note * The "Priority within level" structure is only used to resolve simultaneous requests of the same priority level. * The MD interrupt needs a higher priority then ALL the other interrupts. This is to avoid that a mode change will not be serviced in time and that the setting of the S-curve is not updated in time. When the S-curve settings are not updated in time (after a mode change) the monitor may be damaged.
7 -
6 PVSYNC
5 PT2
4 PS
3 PT1
2 PX1
2 PT0
0 PX0
Table 9-6 Interrupt Priority Register(IP: 0B8H)
RESET VALUE: x0000000B
BIT 7 6 5 4 3 2 1 0
SYMBOL PVSYNC PT2 PS PT1 PX1 PT0 PX0
FUNCTION
Reserved Vsync interrupt priority level Timer2 interrupt priority level Not used Timer1 interrupt priority level External interrupt (INT1) priority level Timer0 interrupt priority level External interrupt (INT0) priority level
Table 9-7 Description of the IP bits
May.2001 ver1.1
27
HMS9xC7132 / HMS9xC7134
7 PDDC
6 -
5 -
4 -
3 -
2 -
2 PI2C
0 PMD
Table 9-8 Interrupt Priority Register(IPA: 0B6H)
RESET VALUE: 0xxxxx00B
BIT 7 6 5 4 3 2 1 0
SYMBOL PDDC PX6 PX5 PX4 PX3 PX2 PI2C PMD
FUNCTION
DDC interrupt priority level Not used Not used Not used Not used Not used I2C interrupt priority level MD interrupt priority level
Table 9-9 Description of the IPA bits
28
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
9.4 How Interrupt are handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this H/W generated LCALL is not blocked by any of the following conditions : * An interrupt of equal priority or higher priority level is already in progress. * The current machine cycle is not the final cycle in the execution of the instruction in progress. * The instruction in progress is RETI or any access to the interrupt priority or interrupt enable registers. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if an interrupt flag is active but being responded to for one of the above mentioned conditions, if the flag is still inactive when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate service routine. The hardware generated LCALL pushes the contents of the Program Counter on to the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to as shown in Table 9-10. Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that the interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also return execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible.
SOURCE INT0 MD Timer0 I2C INT1 DDC Timer1 VSYNC Timer2
VECTOR ADDRESS 0003H 004BH 000BH 0043H 0013H 003BH 001BH 0033H 002BH Table 9-10 Vector addresses
May.2001 ver1.1
29
HMS9xC7132 / HMS9xC7134
10. POWER-SAVING MODE
Two software selectable modes of reduced power consumption are implemented. * Idle mode * Power-down mode
The following functions are switched off when the microcontroller enters the Idle mode. * CPU (halted) * I2C interface (halted) * PWM0 to PWM7 and DPWM0 to DPWM2 (reset, output = High) * 8-bit ADC (aborted if conversion in progress)
The following functions remain active during Idle mode. These functions may generate an interrupt or reset and thus terminate the Idle mode. * Timer0, Timer1 and Timer2 * Watchdog timer * DDC interface * External interrupt * Mode detection
In Power-down mode, the system clock is halted. Both the oscillator will be stopped after setting the bit PD in PCON.
10.1 Power control register
The modes Idle and Power-down are activated by software via the PCON register.
7 -
6 -
5 LVREN
4 LVRLS
3 GF1
2 GF0
2 PD
0 IDL
Table 10-1 Power control Register(PCON:87H) BIT 7 to 6 5 4 3 2 1 0 SYMBOL LVREN LVRLS GF1 GF0 PD IDL
RESET VALUE:xx000000B FUNCTION
Not used Enable low voltage reset Select low VDD level ; 3.7V or 3.5V General purpose flag bit General purpose flag bit Activate Power-down mode Activate Idle mode
Table 10-2 Description of the PCON bits
30
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
MODE Idle
MEMORY Intenal
PORT0-3 Data Data
SYNC on High
PWM High High
I2C High-Z High-Z
DDC on High-Z
-
-
Power-down Intenal
Table 10-3 External Pin Status During Idle and Power-down modes
10.2 Idle mode
The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before idle mode is activated. Once in the idle mode, the CPU status is preserved in its entirety : Stack pointer, Program counter, Program status word, Accumulator, RAM and All other registers maintain their data during idle mode. There are three ways to terminate the idle mode. * Activation of any enabled interrupt X0, T0, X1, T1 etc. will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following return from interrupt instruction RETI, the next instruction to be executed will be the one which follows the instruction that wrote a logic 1 to PCON.0. * External hardware reset : the hardware reset is required to be active for two machine cycle to complete the reset operation. * Internal watchdog reset : the microcontroller restarts after 3 machine cycles in all cases.
10.3 Power-down mode
The instruction that sets PCON.1 is the last executed prior to going into the Power-down mode. Once in Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the Special Function Register are preserved. The power-down mode can be terminated by an external RESET in the same way as in the 80C51 (but SFRs are cleared due to RESET).
May.2001 ver1.1
31
HMS9xC7132 / HMS9xC7134
11. I/O PORTS
The HMS9xC7132 has four 8-bit ports (Port0, Port1, Port2 and Port3). Port0 - Port3 are the same as in the 80C51, with the exception of the additional functions of Port1, Port2 and Port3. All ports are bidirectional and Pins of which the alternative function is not used may be used as normal bidirectional I/Os except Port3.2, Port3.3 and Port3.5(These Pins can be only used as the output). The use of Port1- Port3 pins as alternative functions are carried out automatically by the HMS9xC7132 provided the associated SFR bit is set HIGH.Port0 is the type of open-drain I/O. Port0.6 and Port0.7 have the capability to drive LED. Fig. 11.1 shows the port structure.
Enable / Data
Port Data Special Data / Gnd Special Function Select Input Data
0 1
I/O PIN
Figure 11-1 Standard output with the open-drain port
The alternative function for Port1, Port2 and Port3 can be described as follows. * Port 0 : No alternative function. * Port 1 : P1.0 is combined with the SCL1 interface line(open-drain) P1.1 is combined with the SDA1 interface line (open-drain) P1.2 is combined with the ACH0 interface line (high-z) P1.3 is combined with the ACH1 interface line (high-z) P1.4 is combined with the ACH2 interface line (high-z) P1.5 is combined with the ACH3 interface line (high-z) P1.6 is combined with the SCL2 interface line (open-drain) P1.7 is combined with the SDA2 interface line (open-drain) * Port 2 : P2.0 is combined with the dynamic PWM0 interface line(open-drain or push-pull) P2.1 is combined with the dynamic PWM1 interface line (open-drain or push-pull) P2.2 is combined with the static PWM0 interface line (open-drain or push-pull) P2.3 is combined with the static PWM1 interface line (open-drain or push-pull) P2.4 is combined with the static PWM2 interface line (open-drain or push-pull) P2.5 is combined with the static PWM3 interface line (open-drain or push-pull) P2.6 is combined with the static PWM4 interface line (open-drain or push-pull) P2.7 is combined with the static PWM5 interface line (open-drain or push-pull) * Port 3 : P3.0 has not alternative function. P3.1 has not alternative function. P3.2 is combined with the HSYNCout interface line (push-pull) P3.3 is combined with the VSYNCout interface line (push-pull) P3.4 is combined with the PWM6 interface line (open-drain or push-pull) P3.5 is combined with the CLAMP or PWM7 interface line (push-pull) P3.6 is combined with the PATOUT interface line (push-pull) P3.7 is combined with the SOG interface line (pull-up)
32
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
11.1 Pin function selection
Special function selection Registers(PxSFS)
Several SFR(P1SFS/P2SFS/P3SFS)s are used to select the port-function or the alternative function of the external pin. * P1SFS(Port1 special function selection register)
7 P1SFS7
6 P1SFS6
5 P1SFS5
4 P1SFS4
3 P1SFS3
2 P1SFS2
2 P1SFS1
0 P1SFS0
Table 11-1 P1SFS bits(91H) BIT SYMBOL FUNCTION RESET
The selection of the pin function.
7 P1SFS7
0 : pin 9 has P1.7 function. 1 : pin 9 has SDA2 function. The selection of the pin function.
0
6
P1SFS6
0 : pin 10 has P1.6 function. 1 : pin 10 has SCL2 out function. The selection of the pin function.
0
5
P1SFS5
0 : pin 20 has P1.5 function. 1 : pin 20 has ACH3 out function. The selection of the pin function.
0
4
P1SFS4
0 : pin 21 has P1.4 function. 1 : pin 21 has ACH2 out function. The selection of the pin function.
0
3
P1SFS3
0 : pin 22 has P1.3 function. 1 : pin 22 has ACH1 out function. The selection of the pin function.
0
2
P1SFS2
0 : pin 23 has P1.2 function. 1 : pin 23 has ACH0 out function. The selection of the pin function.
0
1
P1SFS1
0 : pin 24 has P1.1 function. 1 : pin 24 has SDA1 out function. The selection of the pin function.
0
0
P1SFS0
0 : pin 25 has P1.0 function. 1 : pin 25 has SCL1 out function.
Table 11-2 Description of the P1SFS bits
0
May.2001 ver1.1
33
HMS9xC7132 / HMS9xC7134
* P2SFS(Port2 special function selection register)
7 P2SFS7
6 P2SFS6
5 P2SFS5
4 P2SFS4
3 P2SFS3
2 P2SFS2
2 P2SFS1
0 P2SFS0
Table 11-3 P2SFS bits(92H) BIT SYMBOL FUNCTION RESET
The selection of the pin function.
7 P2SFS7
0 : pin 34 has P2.7 function. 1 : pin 34 has PWM5 function. The selection of the pin function.
0
6
P2SFS6
0 : pin 35 has P2.6 function. 1 : pin 35 has PWM4 out function. The selection of the pin function.
0
5
P2SFS5
0 : pin 36 has P2.5 function. 1 : pin 36 has PWM3 out function. The selection of the pin function.
0
4
P2SFS4
0 : pin 37 has P2.4 function. 1 : pin 37 has PWM2 out function. The selection of the pin function.
0
3
P2SFS3
0 : pin 38 has P2.3 function. 1 : pin 38 has PWM1 out function. The selection of the pin function.
0
2
P2SFS2
0 : pin 1 has P2.2 function. 1 : pin 1 has PWM0 out function. The selection of the pin function.
0
1
P2SFS1
0 : pin 2 has P2.1 function. 1 : pin 2 has DPWM1 out function. The selection of the pin function.
0
0
P2SFS0
0 : pin 3 has P2.0 function. 1 : pin 3 has DPWM0 out function.
Table 11-4 Description of the P2SFS bits
0
34
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
* P3SFS(Port3 special function selection register)
7 P3SFS7
6 P3SFS6
5 P3SFS5
4 P3SFS4 Table 11-5
3 P3SFS3 P3SFS bits(93H) FUNCTION
2 P3SFS2
2 P3SFS1
0 P3SFS0
BIT
SYMBOL
RESET
The selection of the pin function.
7 P3SFS7
0 : pin 28 has P3.7 function. 1 : pin 28 has SOG input function. The selection of the pin function.
0
6
P3SFS6
0 : pin 29 has P3.6 function. 1 : pin 29 has PATOUT out function. The selection of the pin function.
0
5
P3SFS5
0 : pin 30 has P3.5 function. 1 : pin 30 has CLAMP or PWM7 out function. The selection of the pin function.
0
4
P3SFS4
0 : pin 31 has P3.4 function. 1 : pin 31 has PWM6 out function. The selection of the pin function.
0
3
P3SFS3
0 : pin 32 has P3.3 function. 1 : pin 32 has VSYNCout function. The selection of the pin function.
0
2
P3SFS2
0 : pin 33 has P3.2 function. 1 : pin 33 has VSYNCout function. The selection of the pin function. reserved The selection of the pin function.
0
1
P3SFS1
0
0
P3SFS0
0
reserved
Table 11-6 Description of the P3SFS bits
May.2001 ver1.1
35
HMS9xC7132 / HMS9xC7134
12. OSCIALLTOR
The oscillator circuit of the HMS9xC7132 is a single stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete the oscillator circuit. Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the HMS9xC7132 externally, XTAL1 is driven from an external source and XTAL2 left open-circuit.
Main clock 12MHz
Minimum instruction cycle time (ex:NOP ; fex 12clock is needed) 1uS
XTAL1
10 ~ 16MHz
XTAL2
XTAL1
XTAL2
External clock
Figure 12-1 Oscillator configuration
ideal
reset IC
standard; R=10K
C=10uF (Recommanded)
Vdd
4.2V
reset
Vdd
R
reset
C
36
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
13. RESET
There are three ways to invoke a reset and initialize the HMS9xC7132. Via the external RESET pin Via the Watchdog Timer overflow Via low VDD voltage reset Each reset source will cause an internal reset signal active. The CPU responds by executing an internal reset and puts the internal registers in a defined state.
RESET NC CPU& PERI.
WDT
S
Q
R LVR 2.0ms Timer RSTOUT
Figure 13-1 The reset mechanism
13.1 External reset
The reset pin RESET is connected to a Schmitt trigger for noise reduction. A reset is accomplished by holding the RESET pin LOW for at least 2 machine cycles (24 system clock), while the oscillator is running. An automatic reset can be obtained by switching on VDD, if the RESET pin is connected to GND via a capacitor and to the VDD via resistor. The capacitor should be at least 10uF. The increase of the RESET pin voltage depends on the capacitor. The voltage must remain below the higher threshold for at minimum the oscillator start-up time plus 2 machine cycles.
13.2 Watchdog timer overflow
The length of the output pulse from the WDT is over 2048 machine cycles. In chapter 14, the watchdog timer is described in more detail.
13.3 Low VDD voltage reset
When VDD is below 3.7V, the built-in low voltage detector generates an internal reset signals. The reset signal will be LOW during 2ms @12MHz after the voltage is higher than 3.7V.
May.2001 ver1.1
37
HMS9xC7132 / HMS9xC7134
14. WATCHDOG TIMER
The hardware watchdog timer (WDT) resets the HMS9xC7132 when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the processor running out of control. In the idle mode the watchdog timer and reset circuitry remain active. The WDT consists of a 19-bit counter, the watchdog timer reset(WDTRST) SFR and watchdog key register(WDTKEY).Since the WDT is automatically enabled while the processor is running. the user only needs to be concerned with servicing it.The 19-bit counter overflows when it reaches 524288(3FFFH). The WDT increments once every machine cycle. This means the user must reset the WDT at least every 524288 machine cycles (524ms @12MHz). To reset the WDT the usermust write 01EH and then 0E1H to WDTRST. WDTRST is a write only register. The WDT count cannot be read or written. The watchdog timer is controlled by the watchdog key register, WDTKEY. Only pattern 01010101(=55H), disables the watchdog timer. The rest of pattern combinations will keep the watchdog timer enabled. This security key will prevent the watchdog timer from being terminated abnormally when the function of the watchdog timer is needed. In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the processor while in Idle, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
7 WDTKEY7
6 WDTKEY6
5 WDTKEY5
4 WDTKEY4
3 WDTKEY3
2 WDTKEY2
2 WDTKEY1
0 WDTKEY0
Table 14-1 Watchdog timer key register (WDTKEY : 0AEH) BIT 7 to 0 SYMBOL WDTKEY7 to WDTKEY0
RESET VALUE:00000000B FUNCTION
Enable or disable watchdog timer. 01010101(=55H) : disable watchdog timer. others : enable watchdog timer.
Table 14-2 Description of the WDTKEY bits
7 WDTRST7
6 WDTRST6
5 WDTRST5
4 WDTRST4
3 WDTRST3
2 WDTRST2
2 WDTRST1
0 WDTRST0
Table 14-3 Watchdog timer clear register (WDTRST : 0A6H) BIT 7 to 0 SYMBOL WDTKEY7 to WDTKEY0
RESET VALUE:00000000B FUNCTION
Enable or disable watchdog timer. 01010101(=55H) : disable watchdog timer. others : enable watchdog timer.
Table 14-4 Description of the WDTRST bits Example Program; Watch Dog Timer Reset & WDT_refresh Part Reset: clr EA WDT_refresh: mov mov WDTRST, #1Eh ; Watchdog timer reset WDTRST, #0E1h ; Watchdog timer reset
mov PSW, #00 mov SP, #STACK_DATA; mov WDTKEY, #55h ; Watchdog stop
mov WDTKEY, #0F0h ; Watchdog start ret
38
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
15. TIMER
HMS9xC7132 has two 16-bit timers/counters (Timer0, Timer1) to be placed in 80C51 core and one 16-bit auto-reload timer(Timer2) for dynamic PWM.
15.1 Timer0 and Timer1
The external input pin that the Timer/Counter0 and Timer/ Counter1 in 80C51 core have is eliminated. In the timer function, timer register is incremented every machine cycle. Thus, you can think of it as counting machinecycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. Timer 0, Timer 1 have four operating modes. These modes is selected by bit-pairs(M1, M0) in TMOD.
7 GATE
6 C/T
5 M1
4 M0
3 GATE
2 C/T
2 M1
0 M0
Table 15-1 Timer Mode Control register(TMOD)
RESET VALUE:00000000B
BIT 7,3
SYMBOL GATE
FUNCTION Gating control when set. Timer "x" is enabled only while "INTx" pin is high and "TRx" control bit is set. When cleared Timer"x" is enabled whenever "TRx"control bit is set. Timer or Counter selector 0 : Timer 1 : Counter, not supported. Operating modes
6,2
C/T
M1, M0 0, 0 0, 1 1, 0 7 to 0 1, 1
8-bit Timer THx" with "TLx" as 5-bit prescaler 16-bit Timer "THx" and "TLx" are cascaded : there is no prescaler 8-bit auto-reload Timer "THx" holds a value which is to be reloaded into "TLx" each time it overflows. Timer0 : TL0 is an 8-bit Timer controlled by the standard Timer 0 control bit. : TH0 is an 8-bit timer only controlled by Timer 1 control bit. Timer1 : Timer 1 stopped.
Table 15-2 Description of the TMOD bits
May.2001 ver1.1
39
HMS9xC7132 / HMS9xC7134
7 TF1
6 TR1
5 TF0
4 TR0
3 IE1
2 IT1
2 IE0
0 IT0
Table 15-3 Timer Control register(TCON) BIT 7 6 5 4 3 2 SYMBOL TF1 TR1 TF0 TR0 IE1 IT1
RESET VALUE:00000000B FUNCTION
Timer1 overflow flag. Set by hardware on Timer oveflow. Cleared by hardware when processor vectors to interrupt routine. Timer1 run control bit. Set/cleared by software to turn Timer on/off . Timer0 overflow flag. Set by hardware on Timer oveflow. Cleared by hardware when processor vectors to interrupt routine. Timer0 run control bit. Set/cleared by software to turn Timer on/off . Interrupt1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt1 type control bit. Set/cleared by software to specified falling edge/low level triggered external interrupts.
1
IE0
Interrupt0 edge flag. Set by hardware when external interrupt edge detected.
Cleared when interrupt processed. Interrupt0 type control bit. Set/cleared by software to specified falling edge/low level triggered external interrupts. Table 15-4 Description of the TCON bits
0
IT0
15.2 TIMER2
Timer2 is a 16-bit auto-reload timer. The 16-bit capture mode, baud rate generation mode and an event counter function that the Timer/Counter2 in 80C52 core has are eliminated. Since the clock of this timer comes from the system oscillator, Timer2 can be used to count a time period more accurately comparing with Timer0 and Timer1, but the longest period is limited as 65536 x (tOSC/2). The interval between interrupt = 65536 x (2 x tOSC) - (RC2H x 256 + RC2L) x (2 x tOSC) The maximum interrupt period = 65536 x (2 x tOSC)
7 TF2
6 -
5 -
4 -
3 -
2 TR2
2 -
0 -
Table 15-5 Timer2 control register (T2CON : 0C8H) BIT 7 6 to 3 2 1 to 0 SYMBOL TF2 TR2 TR0
RESET VALUE:0xxxx0xxB FUNCTION
Timer2 overflow flag. Set by hardware on Timer overflow. Must be cleared by software. Reserved Timer2 run control bit. set/cleared by software to turn Timer on/off. Reserved Table 15-6 Description of the TCON bits
40
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
7 RC2H7
6 RC2H6
5 RC2H5
4 RC2H4
3 RC2H3
2 RC2H2
2 RC2H1
0 RC2H0
Table 15-7 Reload/Capture high register (RC2H : 0CBH) BIT 7 to 0 SYMBOL RC2H7 to RC2H0
RESET VALUE:00000000B FUNCTION
Reload low register bit7 to bit0
7 RC2L7
6 RC2L6
5 RC2L5
4 RC2L4
3 RC2L3
2 RC2L2
2 RC2L1
0 RC2L0
Table 15-8 Reload/Capture low register (RC2L : OCAH) BIT 7 to 0 SYMBOL RC2L7 to RC2L0
RESET VALUE:00000000B FUNCTION
Reload low register bit7 to bit0
Example Program; Timer Initial & Timer1 Interrupt part initial: ; mov IP, #00h; Interrupt Priority mov PCON, #00; mov TCON, #01010000B; T1, T0 enable mov TMOD, #00010001B; 16 bit timer set mov IE, #11001000B; Global En(7), Vsync(6), Timer1(3) T1_Isr: push PSW; PSW push DPH; DPTR push DPL; push ACC; A push 00h; R0 push 01h; R1 push 02h; R2 mov TH1, #0F0h; F060h to Generate 4mSec mov TL1, #60h;
May.2001 ver1.1
41
HMS9xC7132 / HMS9xC7134
16. DDC INTERFACE
The monitor typically includes a number of user controls to set picture size, position, color balance, brightness and contrast.Furthermore, to optimize some internal setting for different display modes, the timing characteristics should be acquired by the control side. In these days, it is getting popular for these controls to go to PC host. Therefore the communication between monitor and host becomes issue.DDC1, DDC2B, DDC2B+, and DDC2AB(ACCESS.bus) emerge as a standard for monitor interface. A transmitter clocked by incoming VSYNC is dedicated for DDC1 operation. An I2C interface hardware logic forms the kernel of DDC2B, DDC2B+, and DDC2AB. An address pointer, with post increment capability is employed to serve DDC1, DDC2B,DDC2B+ and DDC2AB modes. The conceptual block diagram is illustrated in Fig. 16.1
DDC2B/DDC2AB DDC2B+ Interface
7 Monitor Address S1ADR0 Monitor Address S1ADR1
1
0
SDA1 S1DAT Arbitration Logic SCL1
Shift Register
Bus Clock Generator
Internal Bus
S1CON
RAMBUF
S1STA DDC1/DDC2 Detection
DDC1 Hold Register DDCDAT DDC1 transmitter
RAM Buffer
VSYNCIN Address Pointer Initialization synchronization DDCADR
X
EX_ DAT
SW ENB
X
DDC1 DDC1 INT EN
SWH INT
M0
INTR (From S1STA)
DDCCON INT
Figure 16-1 DDC Interface block diagram
42
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
16.1 The Special Function register for DDC Interface.
Eight SFR : S1CON, S1STA, S1DAT, S1ADR, RAMBUF, DDCCON, DDCADR, DDCDAT. S1CON, S1STA, S1DAT, S1ADR are just the copies of the corresponding registers in general I2C-bus interface.
7 -
6 EX_DAT
5 SWENB
4 -
3 DDCINT
2 DDC1EN
2 SWHINT
0 M0
Table 16-1 DDC mode status and DDC1 control register (DDCCON : 0D7H)
RESET VALUE:x00x0000B
BIT 7
SYMBOL -
FUNCTION Reserved This bit defines the size of the EDID data. It is related to the function of the post increment of the address pointer, DDCADR. When the upper limit is reached, the DDCADR will wrap around to 00H.
6
EX_DAT (R/W)
If EX_DAT is 1: The data size is 256 byte. 0: The data size is 128 byte(The addressing range for the EDID data buffer is mapped from 0 to 127 ; the rest, 128 to 255 , can still be used by the system). This bit indicates if the software/CPU is needed to take care of the operation of DDC1 protocol. If SWENB is
5
SWENB (R/W)
1 : In DDC1 protocol, CPU is interrupted during the period of the 9th transmitting bit so that the S/W service routine can update the hold register of transmitter by moving new data from appropriate area(it is not necessary to be the RAM buffer which is pointed by DDCADR) to the register DDCDAT. This transmitting must be done within 40us. 0 : The hold register of the transmitter will be automatically updated from the RAM buffer without the intervention of CPU.
4
-
Reserved Interrupt Request Bit. This bit is only valid in DDC1 protocol while S/W handling is enabled. This bit is set by H/W and should be cleared by S/W in interrupt service routine. 1 : Interrupt request is pending. 0 : No interrupt request DDC1 enable control bit. If DDC1EN is
3
DDC1INT (R/W)
2
DDC1EN (R/W)
1 : DDC1 is enabled. 0 : DDC1 is disabled ; The activity on VSYNC is ignored. Interrupt Request Bit. This bit is set by H/W when DDC interface switches from DDC1 to DDC2 (i.e. The voltage transient from high to low is observed on SCL1 pin). This bit should be cleared by S/W in interrupt service routine. 1 : Interrupt request is pending. 0 : No interrupt request DDC mode indication bit. This bit will be set by H/W when the voltage transient from high to low is observed on SCL1 pin. Once mode changes into DDC2 mode, the mode is reserved until power is off. 0: DDC1 is set. 1: DDC2 is set. Table 16-2 Description of the DDCCON bits
1
SWHINT (R/W)
0
M0 (R/W)
May.2001 ver1.1
43
HMS9xC7132 / HMS9xC7134
DDC1 DATA register for transmission (DDCDAT : 0D5H) * 8bit read and write register. * Indicates DATA BYTE to be transmitted in DDC1 protocol. Address pointer for DDC interface (DDCADR : 0D6H) * 8bit read and write register. * Address pointer with the capability of the post increment. After each access to RAMBUF register(either by software or by hardware DDC1 interface), the content of this register will be increased by one. It's available-
both in DDC1, DDC2 (DDC2B, DDC2B+, and DDC2AB) and system operation. Host type detection The detection procedure conforms to the sequences proposed by VESA Monitor Display Data Channel(DDC) specification.The monitor needs to determine the type of host system: * * DDC1 or OLD type host. DDC2B host (Host is master, monitor is always slave)
* DDC2B+/DDC2AB(ACCESS.bus) host.
44
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
The monitor where HMS9xC7132 resides is always both DDC1 and DDC2 capable with DDC2 having the higher priority. Thedisplay shall start transmitting DDC1 signals whenever it is powered on and the vertical sync signal is applied to it from the hostfor the first time. The display shall switch to DDC2 within 3 system clocks as soon as it sees a high to low transition on the clockline(SCL), indicating that there are DDC2 devices connected to the bus. Under that condition, the mode flag, M0 will be changed from the default setting 0, to 1. Accordingly, the interrupt will be invoked by setting flag, SWHINT as high.
Fig. 16.2 illustrates the concept and interaction between the monitor and the host. After power on, the DDC1EN bit is set by S/W to act as a DDC1 device. Therefore, the mode flag, M0, is set as 0. Following VSYNC as clock, the monitor will transmit EDID data stream to the host. However, if DDC2 clock, SCL clock, is present, the monitor will be switched to DDC2B device with the mode flag setting as 1. Software will judge it is a DDC2B, DDC2B+, or DDC2AB protocol.
Monitor Power on
Communication is idle
Is VSYNC present ?
EDID sent continuously using VSYNC as clock
Is DDC2 clock present ?
Stop sending of EDID, Switch to DDC2 communication mode
DDC2 communication is idle. Monitor is waiting for a command.
Has a command been received ?
Is 2B+/A.B command detected ?
Is command DDC2B command ? Is monitor DDC2B+/DDC2AB capable ?
Respond to DDC2B command
Respond to DDC2B+/ DDC2AB command
Figure 16-2 Host type detection
May.2001 ver1.1
45
HMS9xC7132 / HMS9xC7134
16.2 DDC1 protocol
DDC1 is primitive and a point to point interface. The monitor is always put at "Transmit only" mode.In the initialization phase, 9 clock cycles on VSYNC pin will be given for the internal synchronization.During this period, the SDA pin will be kept at high impedance state. If DDC1 hardware mode is used, the following procedure is recommended to proceed DDC1 operation. Step1 : Reset DDC1EN (by default, DDC1EN is cleared as low after power on reset). Step2 : Set SWENB as high(the default value is zero.) Step3 : Depending on the data size of EDID data, set EX_DAT as low(128 bytes) or high(256bytes). Step4 : By using bulky moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer. Step5 : Reset SWENB to low. Step6 : Reset DDCADR to 00H. Step7 : Set DDC1EN as high. In case SWENB is set as high, interrupt service routine must be finished within 40 machine cycles in 12 MHz system clock. Note : If EX_DAT equals to low, it is meant the lower part is occupied by DDC1 operation and the upper part is still free to the system. Nevertheless, the effect of the post increment just applies to the part related to DDC1 operation. In other words, the system program is still able to address the locations from 128 to 255 in the RAM buffer through MOVX command but without the facility of the post increment. ex) In case of accessing 200 of the RAM Buffer. MOV R0, #200 MOVX A, @R0
SCL VCLK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1
DDC1INT DDC1EN SDA Hi-Z B7 B6 B5 B4 B3 B2 B1 B0 HiZ B7
tSU(DDC1)
tH(VSYNC)
tL(VSYNC)
tDOV
Figure 16-3 Transmission protocol in DDC1 interface.
16.3 DDC2B protocol
DDC2B is constructed base on Philips I2C interface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always regarded as the slave. Both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. In this protocol, address pointer is also used. According to DDC2B specification, A0(for write mode) and A1(for read mode) are assigned as the default address of monitors. The reception of the incoming data in write mode or the updating of the outgoing data in read mode should be finished within the specified time limit. If software in the slaves side cannot react to the master in time, based on I2C protocol, SCL pin can be stretched low to inhibit the further action from the master. The transaction can be proceeded in either byte or burst format.
46
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
DDC Interrupt vector address ( 003BH )
SWENB = 0
Check Mode flag in DDCCON Mode = 1 Mode = 1 Mode = 0 DDC2B+/DDC2AB command received DDC2B command received DDC2B+/DDC2AB Utilities DDC2B Utilities DDC1 Utilities
SWENB = 1
I2C Service Routines
DDC1 Transmitter (H/W)
I2C Interface (H/W)
Figure 16-4 The conceptual structure of DDC Interface
16.4 DDC2AB/DDC2B+ protocol
DDC2AB/DDC2B+ is a superset of DDC2B. Monitors that implement DDC2AB/DDC2B+ are full featured ACCESS.bus devices. Monitor that implement DDC2B+ uses the same command set as DDC2AB but cannot use Access.bus device. Essentially, they are similar to DDC2B. I2C interface forms the fundamental layer for both protocols. The default address for monitors is assigned as 6EH other than A0/A1H in DDC2B. Monitors and hosts can play both the roles of master and slave. Under this kind of protocol, it is easy to extend the support for hosts to read VDIF(VESA Video Display Information Format) and remotely control monitor functions. Command / Information sequence between host and monitor must conform to the specification of ACCESS.bus. Timing rules specified in ACCESS.bus such as maximum response time to RESET message(< 250 ms)form host, maximum time to hold SCL low(< 2ms) etc. can be satisfied through software check and built-in timers such as Timer0, Timer1. In DDC2AB/DDC2B+, monitor itself can act as a monitor to activate the transaction. The default address assigned for host is 50H.
May.2001 ver1.1
47
HMS9xC7132 / HMS9xC7134
16.5 The RAM Buffer and DDC application
RAM Buffer (RAMBUF) : the RAM buffer can be shared as the system RAM or DDC RAM buffer.
MODE 0
EX_DAT 0
SWENB
XRAM : 0 to 127 Normally reserved for DDC1 EDID data (Note 1, Note 2, Note 3)
XRAM : 128 to 255 Available for the system access. (Note 2) Normally reserved for DDC1 EDID data. (Note 1, Note 2, Note 4) Available for the system access.
1
0
Normally reserved for DDC1 EDID data (Note 1, Note 2)
DDC1 0 1 Normally reserved for DDC1 EDID data (Note 3, Note 5) 1 1 Normally reserved for DDC1 EDID data (Note 5) 0 1 Normally reserved for DDC2 EDID data (Note 3) DDC2 1 1 Normally reserved for DDC2 EDID data Normally reserved for DDC2 EDID data. (Note 4) Table 16-3 Description of the EX_DAT and SWENB Note Normally reserved for DDC1 EDID data. (Note 4, Note 5) Available for the system access.
1. READ/WRITE through MOVX instruction might conflict with the access from DDC1 hardware. So, the access from CPU by using MOVX instruction is forbidden. 2. READ/WRITE through DDCADR and RAMBUF registers has the conflicting problem also. Even the content of DDCADR, which should be employed by DDC1 hardware, will be damaged. So, it is inhibited to use this type of access. 3. If DDCADR reaches 127, it will automatically wrap around to 0 after the access is done. 4. If DDCADR reaches 255, it will automatically wrap around to 0 after the access is done. 5. The access conflicting can be avoided because DDC1 access is done by the interrupt service routine. However, the EDID transferring from the RAM buffer should be finished within 40 us.
48
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Example Program;
DDC Interface Initial & Interrupt part
Initial: mov mov mov mov mov mov
DDCCON,#01h DDCADR,#0 DDCCON,#00100100b S1CON,#47h S1ADR0, #0A1h S1ADR1, #41h
; SWENB(0) ; ; 128(6),DDC1_Int(5),DDC1_enable(1) ; 100kHz(011),ENI1(1),ACK_enable(1) ; DDC2B Slave address ; Factory Alignment Host
;================================================================= ; DDC Interface ; 1. ISR S1STA
S1DAT S1CON Refresh ; 2. ISR ; 3. Slaver Receive Address match! S1DAT
S1STA ; Dummy Data
Writing$. Slave Receive ;================================================================= ; task : DDC interrupt Service ; input : Control & Status Peripheral register ;================================================================= DDC_Header: db 00,0FFh,0FFh,0FFh,0FFh,0FFh,0FFh,00 DDC_Isr: push PSW ; push DPH ; push DPL ; push ACC ; push 00 ; push 01 ; mov A, DDCCON ; anl A, #00001000b ; (1) DDC1INT request(bit3=1)? jz DDC2_svc ; ;===================================================== DDC1_mode: mov A, mIICFlag ; anl A,#00000011b ;bUserSoftDDC(1), bDDC1Enable(0) cjne A, #03h, DDC1Enable ; mov A, #0FFh ; mov DDCDAT, A ; ljmp DDC_Int_end ;
" %
. . # &'.
DDC1Enable: mov mov mov cjne mov DDC1_Svc: clr subb jnc mov mov movc sjmp
A, mDDCData DDCDAT, A A, mDDCAddress A, #80h, DDC1_Svc DDCCON, #01h C A, #8 NormalDDC1 DPTR, #DDC_Header A, R0 A, @A+DPTR DDC1_Save
; ; ; ; ; DDC1 Disable,DDC2 Mode ; ; ; ; ; ; ;
NormalDDC1: mov A, #EDID_DATA ; add A, R0 ; data post mov R0, A ; movx A, @R0 ; DDC1_Save: mov DDCDAT, A ; inc mDDCAddress ; ljmp DDC_Int_end ; ;===================================================== DDC2_svc: mov A, DDCCON ; anl A, #00000010b ; (2) SWHINT (SCLLow bit1=1) SCL activity ? jz DDC_I2C_svc ; mov mDDCAddress, #00h ; DDC1 Disable,DDC2 Mode mov DDCCON, #00000001b ; DDC_I2C_svc: mov A, S1STA ; (3) i2C abnormal by G-call,Stop, Arbitration and no Acknowledge mov mI2C_status,A ; anl A, #11000110b ; 1100 011 0 jnz DDC_Abnormal ; GC,STOP,INTR,TX_MODE,BUSY,BLOST,/ACK_REP,SLV mov A, S1CON ; anl A, #00001000b ; (4) Host address matched ? jnz ADDR_Match ; ljmp DDC2B_svc ; (5) 1 byte data access by DDC2B format Addr_Match: mov DDCCON, #01h ; DDC1 Disable,DDC2 Mode setb bI2C_Dir ; TX mov A, S1DAT ; anl A, #0FEh ; LSB BIT MASKING cjne A, #60h, DDC2B_mode ; 60h = Factory Host ?
May.2001 ver1.1
49
HMS9xC7132 / HMS9xC7134
Factory_mode: setb setb mov anl jz ljmp Align_Add_Rx: clr mov mov mov mov mov ljmp
bFactoryMode bService A, mI2C_status A, #10h Align_Add_Rx Align_I2C_Tx bI2C_Dir A, #0 mIICBuffer+pSave, A mIICBuffer+pRead, A S1DAT,#0FFh S1CON, #01000111b DDC_Int_end
; Factory Alignment Host matched 40h ; ; ; ; Slave Receive command ; Slave Transmit command ; RX MCU <== Host ; ; ; ; Dummy write ; i2C enable, Ack out when own slave address in ; Factory Slave Receive start
DDC2B_mode: clr bFactoryMode ; Factory Alignment Host matched cjne A, #0A0h, DDC_Abnormal; A0h = DDC2B Host ? mov A, mI2C_status ; anl A, #10h ; jnz DDC_I2C_Tx ; Slave Transmit clr bI2C_Dir ; mov S1DAT,#0FFh ; Dummy write mov S1CON, #01000111b ; i2C enable, Ack out when own slave address in ljmp DDC_Int_end ; DDC Slave Receive start ;===================================================== DDC2B_svc: ; 1 byte data handling jb bFactoryMode,Line_svc ; mov A, mI2C_status ; anl A, #10h ; jnz DDC_I2C_Tx ; Slave Transmit ; DDC_I2C_Rx: mov A, S1DAT ; Slave-Receive mov mDDCAddress, A ; subaddress catch sjmp DDC_I2C_ref ; DDC_I2C_Tx: mov A, mDDCAddress anl A, #7Fh mov R0,A clr C subb A, #8 mov A, R0 jnc Tx_mode_svc mov DPTR, #DDC_Header movc A, @A+DPTR sjmp Tx_Mode_out ; Slave Transmit ; ; ; ; ; ; ; Header load ; ;
Tx_mode_svc: add A, #EDID_DATA ; 0x80~0xFF mov R0, A ; movx A, @R0 ; Tx_Mode_out: mov S1DAT, A ; EDID data store at S1DAT inc mDDCAddress ; mov S1CON, #47h ; clear ADDR(bit3)11-15 edit mov nI2C_Abn_Cnt,#80h ; no Ack within 128 mSec, P1SFS.1=port sjmp DDC_Int_end ; ===================================================== DDC_Abnormal: mov S1CON, #00000111b ; i2C enable, stop out, Ack out mov nI2C_Abn_Cnt,#0 ; Initial hangup check counter mov P1SFS,#00001111b ; normal I2C hardware interface clr bFactoryMode ; mov DDCCON,#01h ; SWENB(0) mov DDCADR,#0 ; mov DDCCON,#00100100b ; 128(6),DDC1_Int(5),DDC1_enable(1) mov S1CON,#47h ; 100kHz(011),ENI1(1),ACK_enable(1) mov S1ADR0, #0A1h ; DDC2B Slave address mov S1ADR1, #41h ; Factory Alignment Host jnz DDC_I2C_sTx ; DDC_I2C_sRx: mov A,S1DAT sjmp DDC_I2C_ref DDC_I2C_sTx: mov S1DAT,#0FFh DDC_I2C_ref: mov S1CON, #01000111b ;-----------------------------------DDC_Int_end: pop 01 pop 00 pop ACC pop DPL pop DPH pop PSW reti ;-----------------------------------; ; Receive ; ; ; Transmit ; ; i2C enable, Ack out when own slave address in ; ; ; ; ; ; ;
50
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
17. I2C INTERFACE
In the Monitor MCU are two I2C interfaces implemented. * The first one is used by the DDC protocols. * The second one is dedicated for internal connection. With this one its possible to control the video, deflection, convergence and some other functions of the monitor. The serial port supports the twin line I2C-bus, consists of a data line(SDAx) and a clock line(SCLx). * SDA1, SCL1 : the serial port line for DDC Protocol * SDA2, SCL2 : the serial port line for Internal Connection In both I2C interfaces, these lines also function as I/O port lines as follows. * SDA1 / P1.1, SCL1 / P1.0, SDA2 / P1.7, SCL2 / P1.6
The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C serial I/O has complete autonomy in byte handling and operates in 4 modes. * Master transmitter * Master receiver * Slave transmitter * Slave receiver
These functions are controlled by the SFRs. * SxCON : the control of byte handling and the operation of 4 mode. * SxSTA : the contents of its register may also be used as a vector to various service routines. * SxDAT : data shift register. * SxADR : slave address register. Slave address recognition is performed by On-Chip H/W.
7 Slave Address 7 SDAx Arbitration + Sync. Logic Bus Clock Generation 7 Control Register 7 Status Register Shift Register
0 0
Internal Bus
SCLx
0 0
Figure 17-1 The block diagram of the I2C-bus serial I/O.
May.2001 ver1.1
51
HMS9xC7132 / HMS9xC7134
17.1 The Special Function register for I2C Interface.
Serial Control Register(SXCON; S1CON, S2CON)
7 6 5 4 3 2 1 0
CR2
ENI1
STA
STO
ADDR
AA
CR1
CR0
Table 17-1 Serial control register(SxCON; S1CON : 0D8H , S2CON : 0DCH)
BIT 7 6 5 SYMBOL CR2 ENI1 STA FUNCTION This bit along with bits CR1and CR0 determines the serial clock frequency when SIO is in the Master mode. Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high impedance state. START flag. When this bit is set, the SIO H/W checks the status of the I2C-bus and generates a START condition if the bus free. If the bus is busy, the SIO will generate a repeated START condition when this bit is set. STOP flag. With this bit set while in Master mode a STOP condition is generated. When a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO flag. This bit is set when address byte was received. Must be cleared by software. Acknowledge enable signal. If this bit is set, an acknowledge(low level to SDA)is returned during the acknowledge clock pulse on the SCL line when : *Own slave address is received *A data byte is received while the device is programmed to be a Master Receiver *A data byte is received while the device is a selected Slave Receiver. When this bit is reset, no acknowledge is returned. SIO release SDA line as high during the acknowledge clock pulse.
4
STO
3 2
ADDR AA
1 0
CR1 CR0
These two bits along with the CR2 bit determine the serial clock frequency when SIO is in the Master mode.
Table 17-2 Description of the SxCON bits
CR2 0 0 0 0 1
CR1 0 0 1 1 0
CR0 0 1 0 1 0
fosc DIVISOR 16 14 40 60 120
BIT RATE (kHz) at fosc 8MHz 250 285.71 100 66.67 33.33 12MHz 375 428.57 150 100 50 16MHz -
Table 17-3 Selection of the serial clock frequency SCL in Master mode of operation.
52
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Serial Status Register(SXSTA)
SxSTA is a read-only register. The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface are given Table
7
6
5
4
3
2
1
0
GC
STOP
INTR
TX_MODE
BBUSY
BLOST
/ACK_REP
SLV
Table 17-4 Serial status register(SXSTA; S1STA:0D9H, S2STA:0DDH)
BIT 7 6 5 4 3 2 1 SYMBOL GC STOP INTR TX_MODE BBUSY General Call flag. STOP flag. This bit is set when a STOP condition was received. Interrupt flag. This bit is set when a SIO interrupt is requested. Transmission mode flag. This bit is set when the SIO is a transmitter. Otherwise, this bit is reset. Bus busy state flag. This bit is set when the bus is being used by another master. Otherwise, this bit is reset. Bus lost flag. This bit is set when the master loses the bus contention. Otherwise, this bit is reset. Acknowledge response flag. This bit is set when the receiver transmits the not acknowledge signal. This bit is reset when the receiver transmits the acknowledge signal. Slave mode flag. This bit is set when the SIO plays role in the slave mode. Otherwise, this bit is reset. FUNCTION
BLOST /ACK_REP
0
SLV
Table 17-5 Description of SxSTA
Data Shift Register(SXDAT; S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted or data which has just been received. The MSB (bit7) is transmitted or received first; I,e. data shifted from right to left.
7
6
5
4
3
2
1
0
SxDAT7
SxDAT6
SxDAT5
SxDAT4
SxDAT3
SxDAT2
SxDAT1
SxDAT0
Table 17-6 Serial data shift register
Addressing Register(SXADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/ transmitter.
7 6 5 4 3 2 1 0
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
-
Table 17-7 Address register(SLA6 to SLA0 : Own slave address.)
May.2001 ver1.1
53
HMS9xC7132 / HMS9xC7134
17.2 Programmer's Guide for I2C and DDC2
The I2C serial I/O and DDC Interface has operates in 4 modes. * Master transmitter * Master receiver * Slave transmitter * Slave receiver
17.2.1 Master transmitter mode
1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1* then write dummy data to SxDAT. Go to step1. Else then clear STA. 5. Perform required service routines. If this datum == LAST then set STO in SxCON and write last data to SxDAT**. Go to step 6. Else then write next data to SxDAT**. Go to step3. 6. Wait for interrupt. Write dummy data to SxDAT**. * : 1. If the master don't receive the acknowledge from the slave, it generates the STOP condition and returns to the IDLE state. **: 1. This action should be the last in service routine.
Slave transmitter mode
1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write the first data to SxDAT*. Reset AA in SxCON. 5. Wait for interrupt. 6. Read SxSTA. If /ACK_REP == 1** then Go to step7. Else then write the next SxDAT*. Go to step5. 7. Write dummy data to SxDAT*. * : 1. These actions should be the last. **: 1. If the master want to stop the current data requests, it don't have to acknowledge to the slave transmitter. 2. If the slave don't receive the acknowledge from the master, it releases the SDA and enters the IDLE state, so if the master is to resume the data requests, it must regenerate the START condition.
54
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Master receiver mode
1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI1 and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1 then write dummy data to SxDAT Go to step1. Else then clear STA and write FFH to SxDAT. Set AA in SxCON. 5. Wait for interrupt. 6. Read SxSTA. If this datum == LAST then reset AA* and read SxDAT**. Go to step7. Else then read SxDAT**. Go to step5. 7. Wait for interrupt. Read SxSTA. Read SxDAT**. * : 1. If the master want to terminate the current data requests, it don't have to acknowledge to the slave. **: 1. This action should be the last.
Slave transmitter mode
1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write FFH to SxDAT*. 5. Wait for interrupt. 6. Read SxSTA. If STOP == 1 then Go to step7. Else then read data from SxDAT*. Go to step5. 7. Read dummy data from SxDAT*. * : 1. This action should be the last.
May.2001 ver1.1
55
HMS9xC7132 / HMS9xC7134
Master : restart (transmitter)
1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI1 and STA in SxCON. Reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1 then write dummy data to SxDAT. Go to step1. Else then clear STA. 5. Perform required service routines. If this datum == LAST then if RESTART is required then set STA in SxCON and write last data to SxDAT*. Go to step6. Else then set STO in SxCON and write last data to SxDAT*. Go to step7. Else then write next data to SxDAT*. Go to step3. 6. Wait for interrupt. Write slave address to SxDAT*. Go to step3. 7. Wait for interrupt. Write dummy data to SxDAT*. * : 1. This action should be the last in service routine.
56
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
18. PULSE WIDTH MODULATION
18.1 Static PWM
There are eight static PWM in the HMS9xC7132. These channels provide output pulses of programmable duty cycle and polarity. The duty cycle is defined by a counter. The 8-bit counter of a PWM counts modulo 256, i.e. from 0 to 255 inclusive. The value held in the 8-bit counter is compared to the contents of the Special Function Register(PWMn) of the corresponding PWM. The polarity of the PWM outputs is programmable and selected by the PWMLVL bit in PWMCON register. Provided the contents of a PWMn register is equal to or greater than the counter value, the corresponding PWM output is set HIGH (with PWMLVL ="0"). If the contents of this register is less than the counter value, the corresponding PWM output is set LOW(with PWMLVL ="0"). The pulse-width-ratio is therefore defined by the contents of the corresponding Special Function Register(PWMn) of a PWM. By loading the corresponding Special Function Register(PWMn) with either 00H or FFH, the PWM output can be retained at a constant HIGH or LOW level respectively(with PWMLVL = "0"). The PWM outputs PWM0 to PWM7 register share the same pins as Port2.2~Port2.7, Port3.4 and Port3.5 respectively. Selection of the pin function as either a PWM output, a Port line or the other function is achieved by using the appropriate value of P2SF register. The repetition frequency (fPWM) at a PWM output is given by: fPWM = fOSC / (2 x 256)
7
6
5
4
3
2
1
0
PWMLVL
PWM6CFG
PWM5CFG
PWM4CFG
PWM3CFG
PWM2CFG
PWM1CFG
PWM0CFG
Table 18-1 PWM control register (PWMCON : 0A1H)
BIT 7
SYMBOL PWMLVL Polarity selection of the PWMs. 0 : PWM outputs are not inverted. 1 : PWM outputs are inverted.
FUNCTION
6 to 0
PWM6CFG to PWM0CFG
Output type selection of the PWMs. 0 : open-drain type. 1 : push-pull type Table 18-2 Description of the PWMCON bits
May.2001 ver1.1
57
HMS9xC7132 / HMS9xC7134
18.2 Dynamic PWM
There are two dynamic PWMs in the HMS9xC7132. The DPWMs can be used to generate various waveform by software programming, and are used to achieve geometric compensation by generating a parabola output waveform which is synchronized with VSYNCin signal for pin/trap, bow/tilt, vertical linearity or focus compensation in monitor system. This is achieved by utilizing timer2. The low 8-bit in timer2 is used as 8-bit counter for PWM signal and the high 8-bit in timer2 is used to decide the number of PWMs in one video frame. One video frame can be divided to any number of blocks according to the register RC2H value within 256 blocks, and here the RC2L will be 00H for 8-bit PWM resolution. The dynamic PWM outputs DPWM0 to DPWM1 register share the same pins as Port2.0~Port2.1respectively. The repetition frequency (fDPWM) at a DPWM output is given by (in case of RC2L=00H): fDPWM = fOSC / (2 x 256)
7
6
5
4
3
2
1
0
DPWMLVL
-
-
-
-
-
DPWM1CFG DPWM0CFG
Table 18-3 Dynamic PWM control register (DPWMCON : 0B1H) BIT 7 SYMBOL DPWMLVL FUNCTION Polarity selection of the DPWMs. 0 : DPWM outputs are not inverted. 1 : DPWM outputs are inverted. Output type selection of the DPWMs. 0 : open-drain type. 1 : push-pull type Table 18-4 Description of the DPWMCON bits
1 to 0
DPWM1CFG to DPWM0CFG
Vsync
DPWMx VDD
Table 18-5 DPWM application circuit
58
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
Using one Dynamic PWM to compensate the following H size distortion :
1. Pincushion (PCC amplitude)
2. Trapezoid (Keystone)
3. CBOW (Quarter Width)
4. PCC corner
5. S Curve
Using one Dynamic PWM to compensate the following H center distortion :
1. Pin Balance (Bow)
2. Key Balance (Tilt)
3. Corner Balance
May.2001 ver1.1
59
HMS9xC7132 / HMS9xC7134
19. SYNC PROCESSOR
The characteristics of Sync processor are as follows. Automatic mode detection by hardware to capture the following signal characteristics : * Hsync and Vsync frequency measured with 12-bit accuracy (fSH= 12MHz, fSV= 125KHz) * Hsync and Vsync polarity * Hsync and Vsync presence needed for implementing the VESA DPMS standard Integrated composite sync separation Integrated signal generators for generating : * Free running horizontal and vertical sync pulses * Clamping pulse(Back porch, Front porch) * Pattern signal (white picture, black picture, cross hatch and inverse cross hatch) Special option : * Missing sync pulse insertion All measured parameters are stored in Special Function Register such that the data is available at any time. The block diagram of the complete sync processor is given in Figure 19-1
19.1 Sync input signals
The sync inputs are able to handle standard TTL level sync signals. From Figure 19-1 it can be seen that both the HSYNCin and SOGin inputs accept composite sync signals. The HSYNCin and VSYNCin input is meant to be connected to the Hsync and Vsync of the VGA cable while SOGin input is meant to be connected to a sync slicer in order to handle Sync-On-Green at the video input. This last signal should have a TTL level also. The selection between the HSYNCin and the SOGin inputs, as well as the selection between the VSYNCin and separated Vsync, can be done via software.
Select Flag HSEL VSEL 0 : HSYNCin 1 : SOGin
Signal to detector
0 : VSYNCin 1 : Separated VSYNC
Table 19-1 Sync Input selection
19.2 Horizontal polarity correction
In order to simplify the processing in the following stages, the HSYNC polarity correction circuit is able to convert the input sync signals to positive polarity signals in all situations. This correction is achieved by the aid of HPOL and HP. HPOL and HP are only settled down in several horizontal scanning lines or a few milliseconds after power-on or timing mode change.
19.3 Vertical polarity correction
The purpose of the vertical polarity correction is similar to the horizontal polarity correction. To get the correct resultafter power-on or a timing mode change, at least 5 frames is needed.
19.4 Vertical sync separation
This block separates the vertical sync from a composite sync signal. At approximately 1/4 of each HSYNC line the logical level is latched. This yields a slightly delayed vertical sync signal. Special precautions have been taken to suppress equalizing pulses when present and to allow both polarities of the composite signal.The format of the composite sync signal can be standard, as given in Figure 19-2, or can be one of the non standard format as given in Figure 19-3
60
May.2001 ver1.1
May.2001 ver1.1
CPU CPU MDINT VINT fSH CAPTURE SFR CONTROL SFR fSV
HP VP HPOL VPOL HPRES VPRES HSYNC VSYNC HF Change Change VF CONTROL
fOSC
1 / 96
HP
XOR
HSYNCin HSYNC DETECTION
HSYNCout HSYNC GENERATOR
MUX/ CLMP
MUX
SOGin
CLAMP
HSEL V
VP VPOL VPRES
HPOL
SYNC H SEP
HP HPOL HPRES
HPG HP HF HOPOL HOPW VP VF VOPOL VPG VOPW PAT
Figure 19-1 Block diagram of sync processor XOR
PATOUT
VSYNCin
MUX
VSYNC DETECTION
VSYNC GENERATOR
MUX
VSYNCout
HMS9xC7132 / HMS9xC7134
VSEL
VPOL
61
HMS9xC7132 / HMS9xC7134
19.5 Horizontal sync. detection
This block extracts the following parameters from the incoming horizontal or composite sync : * HPER : The number of clock cycles (fSH = 12MHz) between five sync pulses (4 period time), thus the 12 bits value HPER will be equal to ((4 x 12 x 106 / fH) - 1) where fH is the horizontal sync frequency in Hz. * HPOL : The polarity of the sync signal, HPOL will be reset in case of a positive polarity and set in case of a negative polarity. The 1/4 point value of HSYNC period time will be latched for HPOL. * HPRES :To detect the presence of the valid HSYNC signal, Detector measures the time interval between five sync pulses (4 period time). No active sync is coming in if the counter reaches a value of FF0H(4080). * HCHG : The HCHG flag will be set if a change is detected in either the polarity or the period time. To avoid unintended setting of the HCHG flag a small deviation in the period time is allowed.The allowed deviation is approximately 167ns per line.
19.6 Vertical sync. detection
This block extracts the following parameters from the incoming vertical sync: * VPER : Either the number of clock cycles (fSV=125kHz sampling) between two sync pulses(period time). In case the period time is measured this 12 bits VPER will be equal to 125 x 103 / fV where fV is the vertical sync frequency in Hz. * VPOL : The polarity of the sync signal, VPOL will be reset in case of a positive polarity and reset in case of a negative polarity. It should be noted here that in case of a composite sync signal at the input the parameter VPOL will be set always, disregarding the polarity of the incoming composite sync. The 1/4 value of incoming VSYNC value will be latched for VPOL. * VPRES : To detect the presence of the valid VSYNC signal, Detector measures the time interval between two consecutive rising edges of the input signal. No active sync is coming in if the counter reaches a value of FF0H(4080). * VCHG : The VCHG flag will be set if a change is detected in either the polarity or the period time. To avoid unintended setting of the VCHG flag a small deviation in the period time is allowed.The allowed deviation is approximately 32us per line.
Detection input HSYNC input VSYNC input
Threshold frequency 12 KHz 30 Hz
Table 19-2 Threshold frequencies of the presence detector
62
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
CSYNC
HSYNC
VSYNC 2nd field 1st field
CSYNC
HSYNC
VSYNC 1st field 2nd field
Figure 19-2 Standard composite sync signals
HSYNC
VSYNC
CSYNC-1
CSYNC-2
CSYNC-3
CSYNC-4
CSYNC-5
CSYNC-6
Figure 19-3 Non-standard composite sync signals
May.2001 ver1.1
63
HMS9xC7132 / HMS9xC7134
Both the HCHG and the VCHG signals are combined and connected to the internal interrupt. Interrupt will be issued when change is continuously detected like following table.
Due to this fast interrupt the S-correction can be set to a safe level before any damage to the deflection circuitry will occur.
Mode change HPnew < HPpre Period HSYNC Polarity NEG => POS VPnew < VPpre Period VSYNC Polarity NEG => POS VPnew > VPpre To Static State POS => NEG HPnew > HPpre To Static State POS => NEG
Interval between mode change and interrupt HPnew x 61 to (4 x HPnew x 15) - (n x HPpre) (4 x HPnew) x 3 - (n x HPpre) (4 x HPnew) x 3 - (n x HPpre) 60 HSYNC lines 60 HSYNC lines (VPnew x 2 + VPprev) to (Vnew x 3) (VPnew) to (VPnew x 2) (VPnew) to (VPnew x 2) 3 VSYNC lines 2 VSYNC lines
Table 19-3 Time interval between mode change and interrupt Internally there are two 12-bit counter for HSYNC and VSYNC period check , HSYNC counter count up from 0 to 4096 for 4 HSYNC lines according to 12MHz clock, and VSYNC counter count up from 0 to 4096 for one VSYNC line according to 125KHz clock. For HSYNC static state that HSYNC frequency is under 12KHz, counter value is more than 4080 value,and for VSYNC static state that VSYNC frequency is under 32Hz, counter value is more than 4080 value.
64
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
19.7 Horizontal sync. generator
This block generates horizontal sync pulses with positive polarity.This can be done in 3 modes, selectable with HPG. When HPG is 00, the generator operates in the free running mode and the generated pulse repetition period equals HF x 1/12 MHz clock period, where HF is a 10 bit value. As a result the frequency of the free running output sync pulse equals 12 x 106 / HF, with about 12 kHz as lower boundary.When HPG is 01, the input sync pulse is followed and a substitution pulse is inserted. In case HPG equals 11, the inputsync pulse is followed but a substitution pulse is disabled, while the incoming sync is missing.
HPG[1:0] 00
Selected mode Free running mode Period time of horizontal pulse generator (= HF) The same pulse as the input horizontal sync Substitution pulse insertion in case of a missing sync pulse Reserved The same pulse as the input horizontal sync No substitution pulse insertion in case of a missing sync pulse
Table 19-4 Modes of the horizontal pulse generator
01
10
11
HOPW[4:0] 00000 00001 00010 ------11101 11110 11111 2 x 83 ns 3 x 83 ns 4 x 83 ns
Selected mode
Incremented by 83ns (1/12 x 10-6 ) 31 x 83 ns 32 x 83 ns 33 x 83 ns Table 19-5 Free running horizontal sync pulse width
Example Program; Freerun mode
;================================================================ ; Free running ;================================================================ SetFreeRunning: lcall SetVcp SetFreeRunning1: mov A, #01000100b ; rising Edge Interrupt mov MDCON, A ; mov HFH,#00101110b ; Hf = 64.6 kHz mov HFL,#01010000b ; HOPW[10000] mov VFH,#01000010b ; Vf = 60 Hz mov VFL,#11001000b ; VOPW[1000] mov CPGEN,#11100000b ; White Picture Clamping and Pattern mov A, #01000000b ; Negative Hsync, Positive Vsync free-run mov HVGEN, A ; lcall DpmsHLinearity ; ret
May.2001 ver1.1
65
HMS9xC7132 / HMS9xC7134
19.8 Vertical sync. generator
This block generates vertical sync pulses with positive polarity. This can be done in 3 modes, selectable with VPG. When VPG is 00, the generator operates in the free running mode and the generated pulse repetition period equals VF x HF x 1/12 MHz clock period, where VF is a 12 bit value. As a result the frequency of the free running output sync pulse equals 12 x 106 / HF / VF. When VPG is 01, the input sync pulse is followed and a substitution pulse is inserted. In case VPG equals 11, the input sync pulse is followed but a substitution pulse is disabled, while the incoming sync is missing.
VPG[1:0] 00
Selected mode Free running mode Period time of vertical pulse generator (= VF) The same pulse as the input horizontal sync Substitution pulse insertion in case of a missing sync pulse Reserved The same pulse as the input vertical sync No substitution pulse insertion in case of a missing sync pulse
Table 19-6 Modes of the vertical pulse generator
01
10
11
VOPW[3:0] 0000 0001 0010 ------1101 1110 1111 2 x t H(free) 3 x t H(free) 4 x t H(free) Incremented by t H(free) 15 x t H(free) 16 x t H(free) 17 x t H(free)
Selected mode
Table 19-7 Free running vertical sync pulse width
19.9 HSYNC / VSYNC output driver
This is output stage for HSYNCout and VSYNCout. It offers output selection, output enabling/disabling and output polarity selection. With HOPOL and VOPOL the output is selected.
66
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
19.10 Clamp pulse generator
The clamp pulse is generated by setting CLMPEN and always accompanies the HSYNCout pulse, even in the free running mode. This block generates a clamping pulse with programmable pulse width, determined by CPW. It can be started at the front porch (CFB reset) or at the back porch (CFB set), and the polarity can be set with COPOL.
CPW[2:0] 000(11) 001(11) 010(11) 011(11) 100(11) 101(11) 110(11) 111(11) 5 x 83ns 9 x 83ns 13 x 83ns 17 x 83ns 21 x 83ns 25 x 83ns 29 x 83ns 33 x 83ns
Clamping pulse width
Table 19-8 Clamping pulse width
19.11 Pattern generator
This generator is used for test pattern generation when in free running mode.Four picture can be selected : a white, a cross hatch, a balck and inverted cross hatch pictures.When not in free running mode , the output is disabled. The pattern output can be used for burn-in test or e.g. for quick servicing without the need of a video source. The displayed pattern might look different in the different timing modes,symmetric display is not guaranteed.
19.12 Suspend mode
The complete Sync processor can be set into a suspend mode for lowering the power consumption by means of signal MDDN.
MDDN 0 1 Sync. processor is running.(default) Sync. processor is disabled.
Mode
Table 19-9 Suspend mode
7
6
5
4
3
2
1
0
MDDN
CLMPEN
PATEN
-
-
VINTE
HSEL
VSEL
Table 19-10 Mode detection control register.(MDCON : 0F1H)
May.2001 ver1.1
67
HMS9xC7132 / HMS9xC7134
BIT 7 6 5 4 to 3 2
SYMBOL MDDN CLMPEN PATEN VINTE
FUNCTION 0 : hardware mode detection operating normally(default) 1 : hardware mode detection disabled (low power consumption) 0 : clamp pulse out disabled(default) 1 : clamp pulse out enabled 0 : pattern out disabled(default) 1 : pattern out enabled Not used Vsync rising or falling edge interrupt select 0: Vsync rising edge interrupt 1: Vsync falling edge interrupt 0 : HSYNCin 1 : SOGin 0 : VSYNCin 1 : separated VSYNC
Table 19-11 Description of the MDCON bits
1 0
HSEL VSEL
7
6
5
4
3
2
1
0
-
VINT
HPRES
VPRES
HPOL
VPOL
HCHG
VCHG
Table 19-12 Mode detection status register(MDST : 0F2H)
BIT 7 6 5 -
SYMBOL Not used Vsync interrupt flag Indicate the presence of Hsync 0 : not present (Hfreq < 12 kHz) 1 : present ( Hfreq 12 kHz) Indicate the presence of Vsync 0 : not present (Vfreq < 30 Hz) 1 : present ( Vfreq 30 Hz)
FUNCTION
VINT HPRES
4
VPRES
3
HPOL
2
VPOL
1
HCHG
0
VCHG
Indicate the polarity of Hsync/Csync : 0 : positive polarity 1 : negative polarity Indicate the polarity of Vsync : 0 : positive polarity 1 : negative polarity Indicate a change in horizontal period and/or polarity: 0 : no change 1 : change detected Indicate a change in vertical period and/or polarity: 0 : no change 1 : change detected Table 19-13 Description of the MDST bits
68
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
7
6
5
4
3
2
1
0
VP11
VP10
VP9
VP8
VP7
VP6
VP5
VP4
Table 19-14 Vsync period low byte register (VPH : 0F3H)
7
6
5
4
3
2
1
0
HP11
HP10
HP9
HP8
HP7
HP6
HP5
HP4
Table 19-15 Hsync period low byte register (HPH : 0F4H)
7 6 5 4 3 2 1 0
VP3
VP2
VP1
VP0
HP3
HP2
HP1
HP0
Table 19-16 Vsync and Hsync period low high register (VHPL : 0F5H)
7 6 5 4 3 2 1 0
-
HOPOL
HPG1
HPG0
-
VOPOL
VPG1
VPG0
Table 19-17 Hsync and Vsync generation control register.(HVGEN : 0F9H)
BIT 7 6 -
SYMBOL Not used
FUNCTION
HOPOL
Select polarity of the horizontal output pulse 0 : positive polarity 1 : negative polarity Horizontal pulse output modes 00 : free running 01 : missing insertion 10 : reserved 11 : the same pulse as the incoming horizontal sync. Not used Select polarity of the vertical output pulse 0 : positive polarity 1 : negative polarity Vertical pulse output modes 00 : free running 01 : missing insertion 10 : reserved 11 : the same pulse as the incoming vertical sync. Table 19-18 Description of the HVGEN bits
5 to 4
HPG1 to HPG0
3 2
VOPOL
1 to 0
VPG1 to VPG0
May.2001 ver1.1
69
HMS9xC7132 / HMS9xC7134
7
6
5
4
3
2
1
0
VF11
VF10
VF9
VF8
VF7
VF6
VF5
VF4
Table 19-19 Vsync free running output high byte register (VFH : 0FBH)
7 6 5 4 3 2 1 0
VF3
VF2
VF1
VF0
VOPW3
VOPW2
VOPW1
VOPW0
Table 19-20 Vsync free running output low byte register (VFL : 0FCH)
7 6 5 4 3 2 1 0
HF9
HF8
HF7
HF6
HF5
HF4
HF3
HF2
Table 19-21 Hsync free running output high byte register (HFH : 0FDH)
7
6
5
4
3
2
1
0
HF1
HF0
-
HOPW4
HOPW3
HOPW2
HOPW1
HOPW0
Table 19-22 Hsync free running output low byte register (HFL : 0FEH)
7 6 5 4 3 2 1 0
COPOL
CFB
CPW2
CPW1
CPW0
-
PATS1
PATS0
Table 19-23 Clamping and Pattern control register(CPGEN : 0FAH)
BIT 7
SYMBOL COPOL
FUNCTION Select the polarity or level of the clamping pulse: 0 : positive polarity when enabled, static low level when disabled 1 : negative polarity when enabled, static high level when disabled Select the trigger moment of the clamping output pulse : 0 : clamp pulse after FRONT porch of horizontal sync 1 : clamp pulse after BACK porch of horizontal sync Clamp pulse width Not used Select one of the following patterns : 00 : white picture 01 : cross hatch picture 10 : black picture 11 : inverse cross hatch picture
Table 19-24 Description of the CPGEN bits
6
CFB
5 to 3 2 1 to 0
CPW2 to CPW0 PATS1 to PATS0
70
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
20. ANALOG-TO-DIGITAL CONVERTOR (ADC)
The analog to digital converter (A/D) allows conversion of an analog input to a corresponding 8-bit digital value. TheA/D module has four analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to VDD2 of ladder resistance of A/D module. The A/D module has two registers which are the control register ACON and A/D result register ADAT. The register ACON, shown in Table 17.1, controls the operation of the A/D converter module. To use analog inputs, I/O is selected by P1SFS register. The processing of conversion starts when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADAT contains the results of the A/D conversion. When conversion is completed, the result is loaded into the ADAT the A/D conversion status bit ADSF is set to "1". The block diagram of the A/D module is shown in Fig. 17.1. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 13us (@12MHz)
VDD2
Ladder Resistor Decoder
ACH0 ACH1 ACH2 ACH3 Input MUX S/H
Successive Approximation Circuit
ACON
ADAT
INTERNAL BUS
Figure 20-1 A/D block diagram
May.2001 ver1.1
71
HMS9xC7132 / HMS9xC7134
7
6
5
4
3
2
1
0
-
-
ADEN
-
ADS1
ADS0
ADST
ADSF
Table 20-1 ADC control register (ACON : 97H)
BIT 7 to 6 5 -
SYMBOL Reserved
FUNCTION
ADEN
ADC enable bit 0 : ADC shut off and consumes no operating current 1 : enable ADC Reserved Analog channel select Channel0 (ACH0) Channel1 (ACH1) Channel2 (ACH2) Channel3 (ACH3) ADC start bit 0 : force to zero 1 : start an ADC; after one cycle, bit is cleared to "0" ADC status bit 0 : A/D conversion is in process 1 : A/D conversion is completed, not in process Table 20-2 Description of the ACON bits
4 3 to 2
ADS1, ADS0 0, 0 0, 1 1, 0 1, 1 ADST
1
0
ADSF
7
6
5
4
3
2
1
0
ADAT7
ADAT6
ADAT5
ADAT4
ADAT3
ADAT2
ADAT1
ADAT0
Table 20-3 ADC data register (ADAT : 96H) BIT 7 to 6 SYMBOL
ADAT7 to ADAT0
FUNCTION A/D conversion result bit7 to bit0 Table 20-4 Description of the ADAT bits
72
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
21. OPERATION MODE
21.1 OTP MODE
The HMS97C7132 is programmed by using a modified QuickPulse Programming algorithm. The HMS97C7132 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by HME. Table 21-1 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick pulse programming are shown in Figure 21-1 and Figure 21-2. Figure 213 shows the circuit configuration for normal program memory verification.
*Program / Verify algorithms
Any algorithm in agreement with the conditions listed in Table 21-1, and which satisfies the timing specifications is suitable.
MODE Read Signature Program Code Data Verify Code Data Program Encryption Table Program Lock Bit 1 Program Lock Bit 2
RESET 0 0 0 0 0 0
P3.3 0 0 0 0 0 0
P3.5/ PROG 1
P3.2 1 1
INT0/ VPP 1 VPP 1 VPP VPP VPP
P2.7 0 1 0 1 1 1
P2.6 0 0 0 0 1 1
P3.7 0 1 1 1 1 0
P3.6 0 1 1 0 1 0
1
1 1 1 1
Table 21-1 EPROM programming modes Note : 1. "0" = Valid low for that pin, "1"= Valid high for that pin. 2. VPP = 12.75V 3. VDD = 5V
10% during programming and verification. ( 10) and high for a minimum of 10
0.25V
4. P3.5/PROG receives 10 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100
*Program Memory Lock Bits
The two-level Program Lock system consists of 2 Lock Bits and a 64-bytes Encryption Array which are used to protect the program memory against software piracy.
MODE 1 2 3
LB1 U P P
LB2 U U P
Protection Type No program lock features Further programming of the EPROM is disabled Same as mode 2, also verify is disabled
U : unprogrammed, P : programmed
Table 21-2Lock Bit Protection Modes
May.2001 ver1.1
73
HMS9xC7132 / HMS9xC7134
*Encryption Array
Within the EPROM array are 64bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte addressed during a verify, address line are used to select a byte of the Encryption array. This byte is then exclusive NOR-ed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified form. It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
*Reading the Signature Bytes
The HMS97C7132 signature bytes in location 30H and 20H. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7 need to be pulled to a logic low.
Device HMS97C7132
Location 30H 20H
Contents ADH 68H
Remarks Manufacturer ID Device ID
Table 21-3 The Value
*Quick-pulse programming
The setup for micro-controller quick-pulse programming is shown in Figure 21-2. Note that the HMS97C7132 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to port 1, 2 and VSYNCIN, as shown in Figure 21-1. The code byte to be programmed into that location is applied to port 0. RESET, PSEN and pins of port2 and 3 in Table 21.1 are held at the "Program Code Data" levels indicated in Table 21.1. The P3.5/ PROG is pulsed low 10 times as shown Figure 21-2. To program the encryption table, repeat the 10 pulses programming sequence for address 0 through 3F H, using the "Program Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycle will produce only encrypted data. To program the security bits, repeat the 10 pulses programming sequence using the "Program Security Bit" levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that INT0/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free glitches and overshoot.
74
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
0
RESET
HSYNCIN VSYNCIN A14 A13 - A8 0 1 1 0 PULSE 1 1
VDD1 VSS1 XTAL2 XTAL1
P2.0 -P2.5 P2.6 P2.7 P3.2/EA P3.3/PSEN P3.5/PROG P3.6
PGM DATA
P0 INT0/VPP
P3.7 VDD2
12.75 V
VSS2 P1 A7 - A0
Figure 21-1 Programming Configuration
10 PULSES
P3.5/PROG
Min 10s 100s(10 100s(10
Enlarged View
Figure 21-2 PROG Waveform
May.2001 ver1.1
75
HMS9xC7132 / HMS9xC7134
*Program Verification
If Lock Bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory location to be read is applied to port 1, 2 and VSYNCIN as shown in Figure 21-4. The other pins are held at the "Verify Code Data" levels indicated in Table 21.1. The contents of the address location will be emitted on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.
0
RESET
HSYNCIN VSYNCIN A14 A13 - A8 0 0 1 0 1 1 1
VDD1 VSS1 XTAL2 XTAL1
P2.0 -P2.5 P2.6 P2.7 P3.2/EA P3.3/PSEN P3.5/PROG
10k
P3.6 P0 INT0/VPP P3.7 VDD2
PGM DATA 5V
VSS2 P1 A7 - A0
Figure 21-3 Verification Configuration
76
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
EPROM Programming and Verification Characteristics TA = 21
to 27
, Vcc = 5V + 10%,
Vss = 0V
Limit Values Parameter Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low Symbol Min VPP IPP 1/tCLCL 12.5 4 48 tCLCL 48 tCLCL 48 tCLCL 48 tCLCL 48 tCLCL 10 10 90 0 10 Max 13.0 50 6 110 48 tCLCL 48 tCLCL 48 tCLCL V mA MHz s s s s Unit
tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGL tAVQV tELQV tEHQZ tGHGL
PROGRAMMING P1.0 - P1.7 P2.0 - P2.5 VSYNCIN PORT0 ADDRESS
VERIFICATION ADDRESS
// // // //
tAVQV tGHDX tGHAX
DATA IN
DATA OUT
tDVGL tAVGL
10 PULSES
P3.5/PROG
tSHGL tGLGL
INT0/VPP
tGHGL
// //
tGHSL
tEHSH
tELQV
tEHQZ
//
P2.7(ENABLE)
Figure 21-4 EPROM Programming and Verification
May.2001 ver1.1
77
HMS9xC7132 / HMS9xC7134
21.2 64MQFP pinning and Package Dimensions
D P W M 0 * /P 2 .0
D P W M 1 * /P 2 .1
P W M 0 * /P 2 .2
P W M 1 * /P 2 .3 53
64
63
62
61
60
59
58
57
56
55
54
52
P W M 2 * /P 2 .4
H SY N C IN
V S YN C IN
P S EN N
R ES ET
P 3 .0
P 3 .1
EAN
ALE
N .C N .C VDD1 V S S1 X TA L2 X TA L1 B P 2 .7 B P 2 .6 S D A 2* * /P 1 .7 S C L 2 * * /P 1 .6 B P 2 .5 B P 2 .4 P 0 .7 P 0 .6 P 0 .5 P 0 .4 N .C N .C N .C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
51 50 49 48 47 46 45 44
P W M 3 * /P 2 .5 N .C N .C N .C P W M 4 * /P 2 .6 P W M 5 * /P 2 .7 H S Y N C O U T /P 3 .2 V S Y N C O U T /P 3 .3 P W M 6 * /P 3 .4 /IN T 1 B P 2 .0 B P 2 .1 C L A M P /P W M 7 /P 3 .5 /P R O G P A T O U T /P 3 .6 S O G I N /P 3 .7 R STO U T VDD2 V S S2 N .C N .C
H M S97C 7132 YYW W
43 42 41 40 39 38 37 36 35 34 33
A C H 3 /P 1 .5
A C H 2 /P 1 .4
A C H 1 /P 1 .3
A C H 0 /P 1 .2
IN T 0 /V P P
B P 2 .3
B P 2 .2
P 0 .3
P 0 .2
P 0 .1
P 0 .0
S D A * * / 1 .1 1P
NOTE 1. DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION AND DAMBAR PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254mm. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL AT MAXIMUM MATERIAL CONDITION. 2. FORMED LEAD SHALL BE PLANAR WITH RESPECT ANOTHER WITHIN 0.10mm 3. CONTROLLING DIMENSION : MILLIMETER. THIS OUTLINE CONFIRMS TO JEDEC PUBLICATION 95 RESISTRATION MO-112.
3.18 MAX
78
S C L 1* / 1 .0 *P
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
21.3 64MQFP Pin Description
PIN NAME (Alternate) N.C N.C VDD1 VSS1 XTAL2 XTAL1 BP2.7 BP2.6 SDA2 /P1.7 SCL2 /P1.6 BP2.5 BP2.4 P0.7 P0.6 P0.5 P0.4 N.C N.C N.C INT0 /VPP P0.3 P0.2 P0.1 P0.0 BP2.3 BP2.2 ACH3 /P1.5 ACH2 /P1.4 ACH0 /P1.3 ACH0 /P1.2 SDA1 /P1.1 SCL1 /P1.0 N.C N.C VSS2 VDD2 RSTOUT SOGin /P3.7
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
In/Out (Alternate) O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O No connection No connection
Function Basic Alternate
Power supply1(+5V) Ground1 Oscillator output pin for system clock Oscillator input pin for system clock External Access / Emulation port2.7 External Access / Emulation port2.6 General I/O port P1.7 General I/O port P1.6 External Access / Emulation port2.5 External Access / Emulation port2.4 General I/O port P0.7; adapted for LED driver General I/O port P0.6; adapted for LED driver General I/O port P0.5 General I/O port P0.4 No connection No connection No connection External interrupt input0; Programming supply voltage (during OTP programming) General I/O port P0.3 General I/O port P0.2 General I/O port P0.1 General I/O port P0.0 External Access / Emulation port2.3 External Access / Emulation port2.2 General I/O port P1.5 General I/O port P1.4 General I/O port P1.3 General I/O port P1.2 General I/O port P1.1 General I/O port P1.0 No connection No connection Ground2 Power supply2(+5V) RESET or Internal reset out / EH-IC reset signal; active High General I/O port P3.7 Sync on Green input ADC channel3 input ADC channel2 input ADC channel1 input ADC channel0 input I2C serial data I/O port for DDC interface I2C serial clock I/O port for DDC interface I2C serial data I/O port I2C serial clock I/O port
Table 21-4 Port Function Description(64MQFP)
May.2001 ver1.1
79
HMS9xC7132 / HMS9xC7134
PIN NAME (Alternate) PATOUT /P3.6 CLAMP /PWM7 / P3.5 /PROG BP2.1 BP2.0 PWM6 /P3.4 INT1 VSYNCout /P3.3 HSYNCout /P3.2 PWM5 /P2.7 PWM4 /P2.6 N.C N.C N.C PWM3 /P2.5 PWM2 /P2.4 PWM1 /P2.3 HSYNCin VSYNCin PSENN ALE EAN PWM0 /P2.2 DPWM0 /P2.1 DPWM0 /P2.0 P3.1 P3.0 RESET
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
In/Out (Alternate) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I
Function Basic General I/O port P3.6 General output only port P3.5 Program pulse input(during OTP programming) External Access / Emulation port2.1 External Access / Emulation port2.0 General I/O port P3.4 General I/O port P3.3 General I/O port P3.2 General I/O port P2.7 General I/O port P2.6 No connection No connection No connection General I/O port P2.5 General I/O port P2.4 General I/O port P2.3 Horizontal sync input Vertical sync input Program Store Enable Not / Emulation PSEN Address Latch Enable / Emulation ALE External Access Not / Emulation EA General I/O port P2.2 General I/O port P2.1 General I/O port P2.0 General I/O port P3.1 General I/O port P3.0 Reset input 8-bit Pulse Width Modulation output0 8-bit Dynamic Pulse Width Modulation output0 8-bit Dynamic Pulse Width Modulation output1 8-bit Pulse Width Modulation output3 8-bit Pulse Width Modulation output2 8-bit Pulse Width Modulation output1 8-bit Pulse Width Modulation output6; External interrupt input1 Vertical sync output Horizontal sync output 8-bit Pulse Width Modulation output5 8-bit Pulse Width Modulation output4 Pattern out Clamp out ; 8-bit Pulse Width Modulation output7 Alternate
Table 21-4 Port Function Description(64MQFP)
80
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
21.4 Development Tools
The HMS9xC7132 is supported by a full-featured macro assembler / linker , an in-circuit emulator MetaICETM. Product In Circuit Emulators Compiler Debugger Developer MetaICE KEIL C51 Compiler, A51/A251 Assembler/Linker XHP3051.exe (Source-level Debugging) An agency in Korea zeusemtek(www.emtek.co.kr) Hankook MDS(www.hkmds.com)
PC
RS-232
MetaLink iceMASTER-SF
CONVERTER
POD
Monitor Board
POWER
Emulator
Figure 21-5 Developement system Hardware Blockdiagram
May.2001 ver1.1
81
HMS9xC7132 / HMS9xC7134
22. INSTRUCTION SET
The HMS9xC7132 uses a powerful instruction set which permits the expansion of on-chip CPU peripherals and optimizes byte efficiency and execution speed. Assigned opcodes add new highpower operation and permit new addressing modes. The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12MHz oscillator, 64 instructions execute in 1us and 45 instructions execute in 2us. Multiply and divide instructions execute in 4 us. For the description of the Date Addressing modes and Hexadecimal opcode cross-reference see Boolean variable manipulation,Program brranching.
*Arithmatic operations
Mnemonic
Description
Bytes
Cycles
Hex Code
ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC A
A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, Rn A, direct A, @Ri A, #data Rn direct @Ri
add register to A add direct byte to A add indirect RAM to A add immediate data to A add register to A with carry flag add direct byte to A with carry flag add indirect RAM to A with carry flag subtract register from A with borrow subtract direct byte from A with borrow subtract indirect RAM from A with borrow subtract immediate data from A with borrow increment A increment register increment direct byte increment indirect RAM decrement A decrement Rn decrement direct byte decrement indirect RAM increment data pointer multiply A and B divide A by B decimal adjust A
1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 2 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1
2x 25 26,27 24 3x 35 36,37 34 9x 95 96,97 94 04 0x 06,07 14 1x 15 16,17 A3 A4 84 D4
A, #data add immediate data to A with carry flag
DEC A DEC Rn DEC direct DEC @Ri INC DIV DA DTPR AB A MUL AB
82
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
*Logical operations
Mnemonic
Description
Bytes
Cycles
Hex Code
ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC
A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A, Rn A, direct A, @Ri A, #data direct, A direct, #data A A A A A A
AND register to A AND direct byte to A AND indirect RAM to A AND immediate data to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR indirect RAM to A OR immediate data to A OR A to direct byte OR immediate data to direct byte exclusive-OR register to A exclusive-OR direct byte to A exclusive-OR indirect RAM to A exclusive-OR immediate data to A exclusive-OR A to direct byte exclusive-OR immediate data to direct byte clear A complement A rotate A left rotate A left through the carry flag rotate A right rotate A right through the carry flag swap nibbles within A
1 2 1 2 2 3 1 2 1 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1
1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
5x 55 56,57 54 52 53 4x 45 46,47 44 42 43 6x 65 66,67 64 62 63 E4 F4 23 33 03 13 C4
SWAP A *Data transfer
Mnemonic
Description
Bytes
Cycles
Hex Code
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct
move register to A move direct byte to A move indirect RAM to A move immediate data to A move A to register move direct byte to register move immediate data to register move A to direct byte move register to direct byte move direct byte to direct byte
1 2 1 2 1 2 2 2 2 3
1 1 1 1 1 2 1 1 2 2
Ex E5 E6,E7 74 Fx Ax 7x F5 8x 85
May.2001 ver1.1
83
HMS9xC7132 / HMS9xC7134
Mnemonic
Description
Bytes
Cycles
Hex Code
MOV MOV MOV MOV MOV
direct, @Ri direct, #data @Ri, A @Ri, direct @Ri, #data
move indirect RAM to direct byte move immediate data to direct byte move A to indirect RAM move direct byte to indirect RAM move immediate data to indirect RAM move code byte relative to DPTR to A move code byte relative to PC to A move external RAM (8-bit address) to A move external RAM (16-bit address) to A move A to external RAM (8-bit address) move A to external RAM (16-bit address) push direct byte onto stack pop direct byte from stack exchange register with A exchange direct byte with A exchange indirect RAM with A exchange LOW-order digit indirect RAM with A
2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1
2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 4 1 1
86,87 75 F6,F7 A6,A7 76,77 90 93 83 E2,E3 E0 F2,F3 F0 C0 D0 Cx C5 C6,C7 D6,D7
MOV DPTR, #data16 load data pointer with a 16-bit constant MOVC A, @A+DPTR MOVC A, @A+C MOVX MOVX MOVX MOVX PUSH POP XCH XCH XCH XCHD A, @Ri A, @DPTR @Ri, A @DPTR, A direct direct A, Rn A, direct A, @Ri A, @Ri
*Boolean variable manipulation
Mnemonic
Description
Bytes
Cycles
Hex Code
CLR CLR
C bit
clear carry flag clear direct bit set carry flag set direct bit complement carry flag complement direct bit AND direct bit to carry flag AND complement of direct bit to carry flag OR direct bit to carry flag OR complement of direct bit to carry flag move direct bit to carry flag move carry flag to direct bit jump if carry flag is set jump if carry flag is not set jump if direct bit is set jump if direct bit is not set jump if direct bit is set and clear bit
1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3
1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 2 2
C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 40 50 20 30 10
SETB C SETB bit CPL CPL ANL ANL OR OR C bit C, bit C, /bit C, bit C, /bit
MOV C, bit *MOV bit, C JC JB rel bit, rel JNC rel JNB bit, rel JBC bit, rel
Note: * This command is not available under OTP Emulation Mode
84
May.2001 ver1.1
HMS9xC7132 / HMS9xC7134
*Program branching
Mnemonic
Description
Bytes
Cycles
Hex Code
ACALL LCALL RET RETI AJMP LJMP SJMP JMP JZ JNZ CJNE CJNE CJNE CJNE DJNZ DJNZ NOP
addr11 addr16
absolute subroutine call long subroutine call return from subroutine return from interrupt
2 3 1 2 2 3 2 1 2 2 3 3
2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
y1 12 22 32 z1 02 80 73 60 70 B5 B4 Bx B6,B7 Dx D5 00
addr16 addr16 addr16 @A+DPTR rel rel A, direct, rel A, #data, rel
absolute jump long jump short jump(relative address) jump indirect relative to the DPTR jump if A is zero jump if A is not zero compare direct byte to A and jump if not equal compare immediate data to A and jump if not equal
Rn, #data, rel compare immediate data to register and jump if not 3 equal A, @Ri, rel Rn, rel direct, rel compare immediate data to indirect RAM and jump if 3 not equal decrement register and jump if not zero decrement direct byte and jump if not zero no operation 2 3 1
*Data addressing modes
Mnemonic
Description
Rn direct @Ri #data #data16 bit addr16 addr11 rel
working register R0-R7 128 internal RAM locations and any special function register (SFR) indirect internal RAM location addressed by register by register R0 or R1 of the actual register bank 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction direct addressed bit in internal RAM or SFR 16-bit destination address. Used by LCALL and LJMP; the branch will be anywhere within the 64 kbytes Program Memory address space 111-bit destination address. Used by ACALL and AJMP;the branch will be within the same 2 kbytes page of Program Memory as the first byte of the following instruction signed(twoOs complement) 8-bit offset byte. Used by SJMP and all conditional jumps; range is - 128 to + 127 bytes relative to first byte of the following instruction
May.2001 ver1.1
85
HMS9xC7132 / HMS9xC7134
*Hexadecimal opcode cross-reference
Mnemonic
Description
x y z
8, 9, A, B, C, D, E, F 1, 3, 5, 7, 9, B, D, F 0, 2, 4, 6, 8, A, C, E
86
May.2001 ver1.1

▲Up To Search▲

Price & Availability of HMS91C71322

	To Download HMS91C71322 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .